公开(公告)号：US6064225A

公开(公告)日：2000-05-16

申请号：US45128

申请日：1998-03-20

申请人： William B. Andrews ,  Barry K. Britton ,  Kai-Kit Ngai ,  Gary P. Powell ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

发明人： William B. Andrews ,  Barry K. Britton ,  Kai-Kit Ngai ,  Gary P. Powell ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

IPC分类号： H01L21/82 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/17736 ,  H03K19/17792 ,  H03K19/17796

摘要： The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as internal routing resources of each of the two PICs, are programmably connected to a single global-signal spine, and the spine is programmably connected directly to only half of the perpendicular branches. Each of the branches can then connect to the cells in two adjacent rows/columns of the array to provide a global signal to any of the cells in the array while only using a branch per every two rows/columns of the device. The reduced number of spine-to-branch connections reduces the capacitive loading on the spines, thereby increasing the speed at which global signals can be transmitted. In addition, sharing spines between adjacent PICs reduces the number of spines in the FPGA by half, thereby providing additional layout space for other resources. Sharing branches also has the same effect as sharing spines in that the number of branches is reduced by half, also increasing global signal speed. These advantages are achieved without reducing the programming flexibility of the FPGA.

摘要翻译： FPGA具有由可编程输入/输出单元（PIC）环形围绕的可编程逻辑单元（PLC）阵列。 在一个实施例中，每对相邻PICs的焊盘以及两个PIC中的每一个的内部路由资源可编程地连接到单个全局信号脊柱，并且脊柱可编程地直接连接到垂直的一半 分支机构 然后，每个分支可以连接到阵列的两个相邻行/列中的单元格，以向阵列中的任何单元提供全局信号，而仅在设备的每两行/列中使用分支。 减少数量的脊对分支连接减少了脊柱上的电容负载，从而增加了全局信号可以传输的速度。 此外，在相邻PIC之间共享脊椎将FPGA中的脊柱数量减少一半，从而为其他资源提供额外的布局空间。 共享分支也具有与共享刺激相同的效果，因为分支数量减少了一半，也增加了全球信号速度。 这些优点在不降低FPGA的编程灵活性的情况下实现。

公开(公告)号：US6049224A

公开(公告)日：2000-04-11

申请号：US950624

申请日：1997-10-15

申请人： Barry K. Britton ,  Ian L. McEwen ,  Ho T. Nguyen ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

发明人： Barry K. Britton ,  Ian L. McEwen ,  Ho T. Nguyen ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

IPC分类号： H03K19/177 ,  H01L25/00 ,  H03K19/173

CPC分类号： H03K19/17728

摘要： A programmable logic device, such as an FPGA, is implemented using logic cells that have configurable connection schemes between routing resources and logic element input pins. For example, in one embodiment, each logic cell in the device has a flexible input structure that supports two or more different connection schemes, which may or may not involve input sharing, where each logic cell can be individually programmed for any of the available connection schemes when the device is configured. As such, the device can be efficiently programmed to implement the user's specific circuitry. The invention balances the competing goals of (1) reducing routing requirements by limiting the number of connections between routing resources and logic element input pins and (2) providing minimally constrained programming of logic elements.

摘要翻译： 使用在路由资源和逻辑元件输入引脚之间具有可配置连接方案的逻辑单元来实现可编程逻辑器件，例如FPGA。 例如，在一个实施例中，设备中的每个逻辑单元具有灵活的输入结构，其支持两个或多个不同的连接方案，其可以或可以不涉及输入共享，其中每个逻辑单元可以针对任何可用连接进行单独编程 配置设备时的方案。 因此，可以有效地对设备进行编程以实现用户的特定电路。 本发明平衡了（1）通过限制路由资源和逻辑元件输入引脚之间的连接数来减少路由需求的竞争目标，以及（2）提供逻辑元件的最小约束编程。

公开(公告)号：US5986471A

公开(公告)日：1999-11-16

申请号：US950446

申请日：1997-10-15

申请人： Barry K. Britton ,  Kai-Kit Ngai ,  Ho T. Nguyen ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

发明人： Barry K. Britton ,  Kai-Kit Ngai ,  Ho T. Nguyen ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

IPC分类号： H03K19/173 ,  H03K19/00 ,  G06F7/38

CPC分类号： H03K19/17736 ,  H03K19/1736

摘要： The bi-directional (BI-DI) buffers and supplemental logic and interconnect (SLIC) cells are designed to be programmed to operate in different modes in order to implement different kinds of logic circuits. In particular, BI-DI buffers of the present invention support at least five different operational modes. In a first mode (Mode A), the BI-DI buffer generates a logic "1" output, for any input value. In a second mode (Mode B), the BI-DI buffer generates a logic "0" output, for any input value. In a third mode (Mode C), the BI-DI buffer buffers the input signal and generates an output signal equal to the input signal. In a fourth mode (Mode D), the BI-DI buffer buffers the input signal and generates an output signal equal to the inverse of the input signal. In a fifth mode, (Mode E), the BI-DI buffer operates as a conventional tri-state driver. Two or more of the BI-DI buffers can be configured to form more complex logic circuits having two or more inputs. For example, groups of BI-DI buffers can be configured as SLIC cells that are part of the basic logic cells for an FPGA. When used in FPGAs, the BI-DI buffers and SLIC cells make implementation of different kinds of logic circuits more efficient than is the case for conventional FPGAs, including logic circuits like decoders and state machines that have large numbers of inputs. At the same time, the FPGAs retain their efficiencies for implementing logic circuits for which FPGAs have traditionally been very efficient, such as random logic and datapath logic.

摘要翻译： 双向（BI-DI）缓冲器和补充逻辑和互连（SLIC）单元被设计为被编程为以不同的模式操作，以便实现不同种类的逻辑电路。 特别地，本发明的BI-DI缓冲器支持至少五种不同的操作模式。 在第一种模式（模式A）中，BI-DI缓冲区为任何输入值产生逻辑“1”输出。 在第二种模式（模式B）中，BI-DI缓冲区为任何输入值产生逻辑“0”输出。 在第三种模式（模式C）中，BI-DI缓冲器缓冲输入信号并产生等于输入信号的输出信号。 在第四模式（模式D）中，BI-DI缓冲器缓冲输入信号并产生等于输入信号的反相的输出信号。 在第五模式（模式E）中，BI-DI缓冲器作为常规三态驱动器工作。 可以将两个或更多个BI-DI缓冲器配置成形成具有两个或更多个输入的更复杂的逻辑电路。 例如，BI-DI缓冲器的组可以被配置为作为FPGA的基本逻辑单元的一部分的SLIC单元。 当在FPGA中使用时，BI-DI缓冲器和SLIC单元使得不同类型的逻辑电路的实现比传统FPGA更为有效，包括具有大量输入的解码器和状态机的逻辑电路。 同时，FPGA保留了实现FPGA传统上非常有效的逻辑电路的效率，例如随机逻辑和数据通路逻辑。