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    Global signal distribution with reduced routing tracks in an FPGA
    1.
    发明授权
    Global signal distribution with reduced routing tracks in an FPGA 失效
    全局信号分配与FPGA中的路由跟踪减少

    公开(公告)号：US6064225A

    公开(公告)日：2000-05-16

    申请号：US45128

    申请日：1998-03-20

    申请人： William B. Andrews ,  Barry K. Britton ,  Kai-Kit Ngai ,  Gary P. Powell ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

    发明人： William B. Andrews ,  Barry K. Britton ,  Kai-Kit Ngai ,  Gary P. Powell ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

    IPC分类号： H01L21/82 ,  H03K19/177 ,  H01L25/00

    CPC分类号： H03K19/17736 ,  H03K19/17792 ,  H03K19/17796

    摘要： The FPGA has an array of programmable logic cells (PLCs) surrounded by a ring of programmable input/output cells (PICs). In one embodiment, the pads of each pair of adjacent PICs, as well as internal routing resources of each of the two PICs, are programmably connected to a single global-signal spine, and the spine is programmably connected directly to only half of the perpendicular branches. Each of the branches can then connect to the cells in two adjacent rows/columns of the array to provide a global signal to any of the cells in the array while only using a branch per every two rows/columns of the device. The reduced number of spine-to-branch connections reduces the capacitive loading on the spines, thereby increasing the speed at which global signals can be transmitted. In addition, sharing spines between adjacent PICs reduces the number of spines in the FPGA by half, thereby providing additional layout space for other resources. Sharing branches also has the same effect as sharing spines in that the number of branches is reduced by half, also increasing global signal speed. These advantages are achieved without reducing the programming flexibility of the FPGA.

    摘要翻译： FPGA具有由可编程输入/输出单元（PIC）环形围绕的可编程逻辑单元（PLC）阵列。 在一个实施例中，每对相邻PICs的焊盘以及两个PIC中的每一个的内部路由资源可编程地连接到单个全局信号脊柱，并且脊柱可编程地直接连接到垂直的一半 分支机构 然后，每个分支可以连接到阵列的两个相邻行/列中的单元格，以向阵列中的任何单元提供全局信号，而仅在设备的每两行/列中使用分支。 减少数量的脊对分支连接减少了脊柱上的电容负载，从而增加了全局信号可以传输的速度。 此外，在相邻PIC之间共享脊椎将FPGA中的脊柱数量减少一半，从而为其他资源提供额外的布局空间。 共享分支也具有与共享刺激相同的效果，因为分支数量减少了一半，也增加了全球信号速度。 这些优点在不降低FPGA的编程灵活性的情况下实现。

    Bi-directional buffers and supplemental logic and interconnect cells for programmable logic devices
    2.
    发明授权
    Bi-directional buffers and supplemental logic and interconnect cells for programmable logic devices 失效
    用于可编程逻辑器件的双向缓冲器和补充逻辑和互连单元

    公开(公告)号：US5986471A

    公开(公告)日：1999-11-16

    申请号：US950446

    申请日：1997-10-15

    申请人： Barry K. Britton ,  Kai-Kit Ngai ,  Ho T. Nguyen ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

    发明人： Barry K. Britton ,  Kai-Kit Ngai ,  Ho T. Nguyen ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

    IPC分类号： H03K19/173 ,  H03K19/00 ,  G06F7/38

    CPC分类号： H03K19/17736 ,  H03K19/1736

    摘要： The bi-directional (BI-DI) buffers and supplemental logic and interconnect (SLIC) cells are designed to be programmed to operate in different modes in order to implement different kinds of logic circuits. In particular, BI-DI buffers of the present invention support at least five different operational modes. In a first mode (Mode A), the BI-DI buffer generates a logic "1" output, for any input value. In a second mode (Mode B), the BI-DI buffer generates a logic "0" output, for any input value. In a third mode (Mode C), the BI-DI buffer buffers the input signal and generates an output signal equal to the input signal. In a fourth mode (Mode D), the BI-DI buffer buffers the input signal and generates an output signal equal to the inverse of the input signal. In a fifth mode, (Mode E), the BI-DI buffer operates as a conventional tri-state driver. Two or more of the BI-DI buffers can be configured to form more complex logic circuits having two or more inputs. For example, groups of BI-DI buffers can be configured as SLIC cells that are part of the basic logic cells for an FPGA. When used in FPGAs, the BI-DI buffers and SLIC cells make implementation of different kinds of logic circuits more efficient than is the case for conventional FPGAs, including logic circuits like decoders and state machines that have large numbers of inputs. At the same time, the FPGAs retain their efficiencies for implementing logic circuits for which FPGAs have traditionally been very efficient, such as random logic and datapath logic.

    摘要翻译： 双向（BI-DI）缓冲器和补充逻辑和互连（SLIC）单元被设计为被编程为以不同的模式操作，以便实现不同种类的逻辑电路。 特别地，本发明的BI-DI缓冲器支持至少五种不同的操作模式。 在第一种模式（模式A）中，BI-DI缓冲区为任何输入值产生逻辑“1”输出。 在第二种模式（模式B）中，BI-DI缓冲区为任何输入值产生逻辑“0”输出。 在第三种模式（模式C）中，BI-DI缓冲器缓冲输入信号并产生等于输入信号的输出信号。 在第四模式（模式D）中，BI-DI缓冲器缓冲输入信号并产生等于输入信号的反相的输出信号。 在第五模式（模式E）中，BI-DI缓冲器作为常规三态驱动器工作。 可以将两个或更多个BI-DI缓冲器配置成形成具有两个或更多个输入的更复杂的逻辑电路。 例如，BI-DI缓冲器的组可以被配置为作为FPGA的基本逻辑单元的一部分的SLIC单元。 当在FPGA中使用时，BI-DI缓冲器和SLIC单元使得不同类型的逻辑电路的实现比传统FPGA更为有效，包括具有大量输入的解码器和状态机的逻辑电路。 同时，FPGA保留了实现FPGA传统上非常有效的逻辑电路的效率，例如随机逻辑和数据通路逻辑。

    Programmable logic device with logic cells having a flexible input structure
    3.
    发明授权
    Programmable logic device with logic cells having a flexible input structure 失效
    具有逻辑单元的可编程逻辑器件具有灵活的输入结构

    公开(公告)号：US6049224A

    公开(公告)日：2000-04-11

    申请号：US950624

    申请日：1997-10-15

    申请人： Barry K. Britton ,  Ian L. McEwen ,  Ho T. Nguyen ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

    发明人： Barry K. Britton ,  Ian L. McEwen ,  Ho T. Nguyen ,  Satwant Singh ,  Carolyn W. Spivak ,  Richard G. Stuby, Jr.

    IPC分类号： H03K19/177 ,  H01L25/00 ,  H03K19/173

    CPC分类号： H03K19/17728

    摘要： A programmable logic device, such as an FPGA, is implemented using logic cells that have configurable connection schemes between routing resources and logic element input pins. For example, in one embodiment, each logic cell in the device has a flexible input structure that supports two or more different connection schemes, which may or may not involve input sharing, where each logic cell can be individually programmed for any of the available connection schemes when the device is configured. As such, the device can be efficiently programmed to implement the user's specific circuitry. The invention balances the competing goals of (1) reducing routing requirements by limiting the number of connections between routing resources and logic element input pins and (2) providing minimally constrained programming of logic elements.

    摘要翻译： 使用在路由资源和逻辑元件输入引脚之间具有可配置连接方案的逻辑单元来实现可编程逻辑器件，例如FPGA。 例如，在一个实施例中，设备中的每个逻辑单元具有灵活的输入结构，其支持两个或多个不同的连接方案，其可以或可以不涉及输入共享，其中每个逻辑单元可以针对任何可用连接进行单独编程 配置设备时的方案。 因此，可以有效地对设备进行编程以实现用户的特定电路。 本发明平衡了（1）通过限制路由资源和逻辑元件输入引脚之间的连接数来减少路由需求的竞争目标，以及（2）提供逻辑元件的最小约束编程。

    Field programmable gate array with write-port enabled memory
    4.
    发明授权
    Field programmable gate array with write-port enabled memory 失效
    具有写端口使能存储器的现场可编程门阵列

    公开(公告)号：US5623217A

    公开(公告)日：1997-04-22

    申请号：US606702

    申请日：1996-02-26

    申请人： Barry K. Britton ,  Kai-Kit Ngai ,  Satwant Singh

    发明人： Barry K. Britton ,  Kai-Kit Ngai ,  Satwant Singh

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/17704

    摘要： A field programmable gate array includes programmable function units (PFUs) that may function as either a logic block or a random access memory (RAM). Each PFU has a write-port enable input when the PFUs are being used as user RAM units. In addition, each PFU includes a write-strobe input. The write operation is accomplished when both the write-port enable input and the write-strobe input are active. This technique allows a reduction of logic gates and control signal conductors. In many cases, these advantages allow for higher system operating frequencies and more gate capacity at a lower cost.

    摘要翻译： 现场可编程门阵列包括可用作逻辑块或随机存取存储器（RAM）的可编程功能单元（PFU）。 当PFU用作用户RAM单元时，每个PFU都有一个写入口使能输入。 另外，每个PFU都包括写入选通输入。 写入操作是在写入端口使能输入和写入选通输入都有效时完成的。 该技术允许减少逻辑门和控制信号导体。 在许多情况下，这些优点允许以更低的成本实现更高的系统工作频率和更多的门容量。

    Hybrid programmable gate arrays
    5.
    发明授权
    Hybrid programmable gate arrays 失效
    混合可编程门阵列

    公开(公告)号：US6020755A

    公开(公告)日：2000-02-01

    申请号：US938550

    申请日：1997-09-26

    申请人： William B. Andrews ,  Barry K. Britton ,  Thomas J. Hickey ,  Ronald T. Modo ,  Ho T. Nguyen ,  Lorraine L. Schadt ,  Satwant Singh

    发明人： William B. Andrews ,  Barry K. Britton ,  Thomas J. Hickey ,  Ronald T. Modo ,  Ho T. Nguyen ,  Lorraine L. Schadt ,  Satwant Singh

    IPC分类号： H01L21/82 ,  H03K19/177

    CPC分类号： H03K19/17796 ,  H03K19/17732

    摘要： A single integrated circuit (IC) having one or more regions of mask-programmed device (MPD) logic for implementing permanent functions and one or more regions of field-programmable gate-array (FPGA) logic for implementing user-specified functions. The FPGA-type logic provides programming flexibility, while the MPD-type logic provides size, speed, functionality, and dollar cost advantages. In one embodiment, a hybrid IC has an array of programmable logic cells (PLCs) implemented using FPGA-type logic, an application-specific block (ASB) implemented using MPD-type logic, and a ring of pads. Fast interface switch hierarchy (FISH) cells provide the interface between the PLC array and the pads, between the PLC array and the ASB, and between the ASB and the pad ring. Muxes in the FISH cells can be programmed to cause the FISH cells to operate either (1) as programmable interface cells (PICs) that provide a direct interface between the PLC array and the pad ring or (2) as ASB-interface cells (AICs) that (a) provide interfaces between the PLC array and the ASB and (b) control interfaces between the ASB and the pad ring.

    摘要翻译： 具有用于实现永久功能的一个或多个屏蔽编程设备（MPD）逻辑区域的单个集成电路（IC）和用于实现用户指定功能的现场可编程门阵列（FPGA）逻辑的一个或多个区域。 FPGA型逻辑提供编程灵活性，而MPD型逻辑提供了大小，速度，功能和美元成本优势。 在一个实施例中，混合IC具有使用FPGA类型逻辑实现的可编程逻辑单元阵列（PLC）阵列，使用MPD型逻辑实现的特定应用块（ASB）和一个垫环阵列。 快速接口交换层次（FISH）单元提供PLC阵列与PLC之间，PLC阵列与ASB之间以及ASB与焊盘环之间的接口。 可以对FISH单元中的复用器进行编程，以使FISH单元（1）作为可编程接口单元（PIC）来操作，这些可编程接口单元（PIC）可在PLC阵列和焊盘环之间提供直接接口，或（2）作为ASB接口单元（AIC） ）（a）提供PLC阵列和ASB之间的接口，（b）控制ASB和焊盘环之间的接口。

    Field programmable gate array with multi-port RAM
    6.
    发明授权
    Field programmable gate array with multi-port RAM 失效
    具有多端口RAM的现场可编程门阵列

    公开(公告)号：US5559450A

    公开(公告)日：1996-09-24

    申请号：US507957

    申请日：1995-07-27

    申请人： Kai-Kit Ngai ,  Satwant Singh

    发明人： Kai-Kit Ngai ,  Satwant Singh

    IPC分类号： G11C11/41 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17704

    摘要： A field programmable gate array (FPGA) with a programmable function unit (PFU) that includes a look-up table (LUT) for implementing a plurality of functions including first and second RAM cells, and a programmable switching device dedicated to coupling and decoupling the RAM cells. The first and second RAM cells are coupled to respective first and second read/write ports. The RAM cells function individually as single-port RAM cells when decoupled by the switching device. However, the RAM cells share data to function collectively as a dual-port RAM cell when coupled by the switching device. The dual-port RAM cell is accessible by both the first and second read/write ports.

    摘要翻译： 具有可编程功能单元（PFU）的现场可编程门阵列（FPGA），其包括用于实现包括第一和第二RAM单元的多个功能的查找表（LUT），以及专用于耦合和解耦的可编程开关装置 RAM单元。 第一和第二RAM单元耦合到相应的第一和第二读/写端口。 当开关器件分离时，RAM单元单独工作为单端口RAM单元。 然而，当由交换设备耦合时，RAM单元共享作为双端口RAM单元的共同功能。 双端口RAM单元可由第一和第二读/写端口访问。

    FPGA having predictable open-drain drive mode
    7.
    发明授权
    FPGA having predictable open-drain drive mode 失效
    FPGA具有可预测的开漏驱动模式

    公开(公告)号：US6028447A

    公开(公告)日：2000-02-22

    申请号：US899428

    申请日：1997-07-24

    申请人： William B. Andrews ,  James F. Hoff ,  Satwant Singh

    发明人： William B. Andrews ,  James F. Hoff ,  Satwant Singh

    IPC分类号： H01L21/82 ,  H03K19/173 ,  H03K19/177 ,  G06F7/38 ,  H01L25/00

    CPC分类号： H03K19/1736

    摘要： A field-programmable gate array (FPGA) having at least one programmable cell (e.g., an input/output (I/O) cell) having an output node circuit (e.g., a pad circuit) in which the output data signal and the tri-state signal are applied to a multiplexer that drives the tri-state port of an output buffer in the output node circuit. This configuration enables the output node circuit to be configured for open drain drive mode operations in a fast, predictable manner that does not need to rely on the FPGA's general routing resources.

    摘要翻译： 具有至少一个可编程单元（例如，输入/输出（I / O）单元）的现场可编程门阵列（FPGA）具有输出节点电路（例如，pad电路），其中输出数据信号和三 状态信号被施加到驱动输出节点电路中的输出缓冲器的三态端口的多路复用器。 该配置使得输出节点电路能够以不需要依赖于FPGA的通用路由资源的快速，可预测的方式配置为开漏驱动模式操作。

    In-system programming of a non-compliant device using multiple interfaces of a PLD
    8.
    发明授权
    In-system programming of a non-compliant device using multiple interfaces of a PLD 有权
    使用PLD的多个接口的不符合设备的系统内编程

    公开(公告)号：US07397274B1

    公开(公告)日：2008-07-08

    申请号：US11100718

    申请日：2005-04-07

    申请人： Howard Tang ,  Satwant Singh ,  San-Ta Kow

    发明人： Howard Tang ,  Satwant Singh ,  San-Ta Kow

    IPC分类号： H03K19/00 ,  G01R31/28

    CPC分类号： H03K19/17744 ,  G01R31/318516 ,  G01R31/318544 ,  H03K19/17732

    摘要： In one embodiment of the invention, a programmable logic device such as an FPGA includes a programmable fabric; a JTAG interface operable to receive configuration data for programming the fabric; a SPI interface operable to receive and transmit configuration data for programming the fabric; and circuitry coupled to the JTAG and SPI interfaces. The circuitry is operable, without being configured, to transfer configuration data received at the JTAG interface to the SPI interface for transmission to an external device having a SPI interface, such as a serial flash memory.

    摘要翻译： 在本发明的一个实施例中，诸如FPGA的可编程逻辑器件包括可编程结构; JTAG接口，可操作用于接收用于编程织物的配置数据; SPI接口，可操作用于接收和发送用于编程织物的配置数据; 以及耦合到JTAG和SPI接口的电路。 电路可操作，而不被配置，将在JTAG接口处接收到的配置数据传送到SPI接口，以传输到具有诸如串行闪存等SPI接口的外部设备。

    Delay-matched ASIC conversion of a programmable logic device
    9.
    发明授权
    Delay-matched ASIC conversion of a programmable logic device 有权
    可编程逻辑器件的延迟匹配ASIC转换

    公开(公告)号：US07038490B1

    公开(公告)日：2006-05-02

    申请号：US10660814

    申请日：2003-09-12

    申请人： Satwant Singh ,  Cyrus Tsui

    发明人： Satwant Singh ,  Cyrus Tsui

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/177 ,  G06F17/505 ,  G06F17/5054 ,  H01L27/118

    摘要： An ASIC conversion of a programmable logic device (PLD) is provided. The PLD includes a plurality of logic blocks coupled together by a PLD routing structure. The ASIC includes a plurality of logic blocks corresponding on a one-to-one basis with logic blocks in the PLD and a routing structure corresponding to the programmable routing structure of the PLD. Vias or traces are selectively placed in the ASIC so that logical behavior of its logic blocks matches that implemented in the PLD and the signal propagation delay through the ASIC matches the delay through the PLD.

    摘要翻译： 提供了可编程逻辑器件（PLD）的ASIC转换。 PLD包括通过PLD路由结构耦合在一起的多个逻辑块。 ASIC包括与PLD中的逻辑块一一对应的多个逻辑块，以及对应于PLD的可编程路由结构的路由结构。 通常选择性地将放置在ASIC中的逻辑块的逻辑行为与PLD中实现的逻辑块匹配，并且通过ASIC的信号传播延迟与通过PLD的延迟匹配。