公开(公告)号：US08258835B1

公开(公告)日：2012-09-04

申请号：US13161145

申请日：2011-06-15

申请人： Cedric Morand ,  David Canard

发明人： Cedric Morand ,  David Canard

IPC分类号： H03L7/06

CPC分类号： H03L7/1976 ,  H03L7/0898

摘要： A fractional-N frequency synthesizer having a cancellation system for phase discontinuity due to loop gain changes may include a phase detector, a current-changeable charge-pump, a loop filter for providing a tuning signal, a voltage-controlled oscillator (VCO) controlled by the tuning signal for providing a VCO output signal, a divider for providing a divided VCO signal, a modulator for generating a modulating signal for fractional-N functionality, wherein the phase detector has a first input for receiving a reference signal oscillating at a reference frequency; a second input for receiving the divided signal; and the phase detector and charge-pump is configured to compare a phase of the first input and a phase of the second input, and generate a charge-pump current on and off, featuring that the cancellation system is implemented inside the modulator having an additional input defined by the changeable charge-pump current values.

摘要翻译： 具有由于环路增益变化引起的相位不连续性消除系统的分数N频率合成器可以包括相位检测器，电流可变电荷泵，用于提供调谐信号的环路滤波器，控制的压控振荡器（VCO） 通过用于提供VCO输出信号的调谐信号，用于提供分频VCO信号的分频器，用于产生用于分数N功能的调制信号的调制器，其中所述相位检测器具有用于接收参考信号振荡的参考信号的第一输入 频率; 用于接收分频信号的第二输入; 并且所述相位检测器和电荷泵被配置为比较所述第一输入的相位和所述第二输入的相位，并且产生电荷泵浦电流的导通和截止，其特征在于所述抵消系统在所述调制器内部具有额外的 输入由可变电荷泵电流值定义。

公开(公告)号：US08451067B2

公开(公告)日：2013-05-28

申请号：US13156051

申请日：2011-06-08

申请人： Cedric Morand ,  David Canard

发明人： Cedric Morand ,  David Canard

IPC分类号： H03L7/197 ,  H03C3/06 ,  H03M7/32 ,  H03L7/085 ,  H03M7/30 ,  H03B5/30

CPC分类号： H03L7/085 ,  H03B5/30 ,  H03L7/1974 ,  H03M7/3004

摘要： A variable modulus sigma delta (ΣΔ) modulator for a fractional-N frequency synthesizer in accordance with the present invention may include an integer division unit; a pulse-width modulation (PWM) generator, a ΣΔ noise-shaping unit, a first input FRAC for receiving a first programmable integer, and a second input MOD for receiving a second input, wherein the integer division unit is configured to perform a translation from the first input and the second input into a first output FRAC′ and a second output R, the PWM generator is configured to receive the second input MOD and the second output R, and generate a modulated pulse signal, and the ΣΔ noise-shaping unit is configured to receive the first output and the modulated pulse signal, and generate a sequence whose average equals approximately the first input over the second input.

摘要翻译： 根据本发明的用于分数N频率合成器的可变模量ΣΔδ（SigmaDelta）调制器可以包括整数除法单元; 脉冲宽度调制（PWM）发生器，SigmaDelta噪声整形单元，用于接收第一可编程整数的第一输入FRAC和用于接收第二输入的第二输入MOD，其中整数除法单元被配置为执行转换 从第一输入和第二输入到第一输出FRAC'和第二输出R，PWM发生器被配置为接收第二输入MOD和第二输出R，并产生调制脉冲信号，并且SigmaDelta噪声整形 单元被配置为接收第一输出和调制脉冲信号，并且生成其平均值等于第二输入端上的第一输入的序列。

公开(公告)号：US20120313722A1

公开(公告)日：2012-12-13

申请号：US13156051

申请日：2011-06-08

申请人： Cedric MORAND ,  David Canard

发明人： Cedric MORAND ,  David Canard

IPC分类号： H03K7/08

CPC分类号： H03L7/085 ,  H03B5/30 ,  H03L7/1974 ,  H03M7/3004

摘要： A variable modulus sigma delta (ΣΔ) modulator for a fractional-N frequency synthesizer in accordance with the present invention may include an integer division unit; a pulse-width modulation (PWM) generator, a ΣΔ noise-shaping unit, a first input FRAC for receiving a first programmable integer, and a second input MOD for receiving a second input, wherein the integer division unit is configured to perform a translation from the first input and the second input into a first output FRAC′ and a second output R, the PWM generator is configured to receive the second input MOD and the second output R, and generate a modulated pulse signal, and the ΣΔ noise-shaping unit is configured to receive the first output and the modulated pulse signal, and generate a sequence whose average equals approximately the first input over the second input.

摘要翻译： 根据本发明的用于分数N频率合成器的可变模量Σ-Δ调制器（＆Sgr＆amp; Dgr））可以包括整数除法单元; 脉冲宽度调制（PWM）发生器，＆Sgr＆amp; Dgr; 噪声整形单元，用于接收第一可编程整数的第一输入FRAC和用于接收第二输入的第二输入MOD，其中所述整数除法单元被配置为执行从所述第一输入和所述第二输入到第一输出的转换 FRAC'和第二输出R，PWM发生器被配置为接收第二输入MOD和第二输出R，并产生调制脉冲信号，并且＆S＆amp; Dgr; 噪声整形单元被配置为接收第一输出和调制脉冲信号，并且生成其平均值等于第二输入上的第一输入的序列。