公开(公告)号：US08451067B2

公开(公告)日：2013-05-28

申请号：US13156051

申请日：2011-06-08

申请人： Cedric Morand ,  David Canard

发明人： Cedric Morand ,  David Canard

IPC分类号： H03L7/197 ,  H03C3/06 ,  H03M7/32 ,  H03L7/085 ,  H03M7/30 ,  H03B5/30

CPC分类号： H03L7/085 ,  H03B5/30 ,  H03L7/1974 ,  H03M7/3004

摘要： A variable modulus sigma delta (ΣΔ) modulator for a fractional-N frequency synthesizer in accordance with the present invention may include an integer division unit; a pulse-width modulation (PWM) generator, a ΣΔ noise-shaping unit, a first input FRAC for receiving a first programmable integer, and a second input MOD for receiving a second input, wherein the integer division unit is configured to perform a translation from the first input and the second input into a first output FRAC′ and a second output R, the PWM generator is configured to receive the second input MOD and the second output R, and generate a modulated pulse signal, and the ΣΔ noise-shaping unit is configured to receive the first output and the modulated pulse signal, and generate a sequence whose average equals approximately the first input over the second input.

摘要翻译： 根据本发明的用于分数N频率合成器的可变模量ΣΔδ（SigmaDelta）调制器可以包括整数除法单元; 脉冲宽度调制（PWM）发生器，SigmaDelta噪声整形单元，用于接收第一可编程整数的第一输入FRAC和用于接收第二输入的第二输入MOD，其中整数除法单元被配置为执行转换 从第一输入和第二输入到第一输出FRAC'和第二输出R，PWM发生器被配置为接收第二输入MOD和第二输出R，并产生调制脉冲信号，并且SigmaDelta噪声整形 单元被配置为接收第一输出和调制脉冲信号，并且生成其平均值等于第二输入端上的第一输入的序列。

公开(公告)号：US08258835B1

公开(公告)日：2012-09-04

申请号：US13161145

申请日：2011-06-15

申请人： Cedric Morand ,  David Canard

发明人： Cedric Morand ,  David Canard

IPC分类号： H03L7/06

CPC分类号： H03L7/1976 ,  H03L7/0898

摘要： A fractional-N frequency synthesizer having a cancellation system for phase discontinuity due to loop gain changes may include a phase detector, a current-changeable charge-pump, a loop filter for providing a tuning signal, a voltage-controlled oscillator (VCO) controlled by the tuning signal for providing a VCO output signal, a divider for providing a divided VCO signal, a modulator for generating a modulating signal for fractional-N functionality, wherein the phase detector has a first input for receiving a reference signal oscillating at a reference frequency; a second input for receiving the divided signal; and the phase detector and charge-pump is configured to compare a phase of the first input and a phase of the second input, and generate a charge-pump current on and off, featuring that the cancellation system is implemented inside the modulator having an additional input defined by the changeable charge-pump current values.

摘要翻译： 具有由于环路增益变化引起的相位不连续性消除系统的分数N频率合成器可以包括相位检测器，电流可变电荷泵，用于提供调谐信号的环路滤波器，控制的压控振荡器（VCO） 通过用于提供VCO输出信号的调谐信号，用于提供分频VCO信号的分频器，用于产生用于分数N功能的调制信号的调制器，其中所述相位检测器具有用于接收参考信号振荡的参考信号的第一输入 频率; 用于接收分频信号的第二输入; 并且所述相位检测器和电荷泵被配置为比较所述第一输入的相位和所述第二输入的相位，并且产生电荷泵浦电流的导通和截止，其特征在于所述抵消系统在所述调制器内部具有额外的 输入由可变电荷泵电流值定义。

公开(公告)号：US20120313722A1

公开(公告)日：2012-12-13

申请号：US13156051

申请日：2011-06-08

申请人： Cedric MORAND ,  David Canard

发明人： Cedric MORAND ,  David Canard

IPC分类号： H03K7/08

CPC分类号： H03L7/085 ,  H03B5/30 ,  H03L7/1974 ,  H03M7/3004

摘要： A variable modulus sigma delta (ΣΔ) modulator for a fractional-N frequency synthesizer in accordance with the present invention may include an integer division unit; a pulse-width modulation (PWM) generator, a ΣΔ noise-shaping unit, a first input FRAC for receiving a first programmable integer, and a second input MOD for receiving a second input, wherein the integer division unit is configured to perform a translation from the first input and the second input into a first output FRAC′ and a second output R, the PWM generator is configured to receive the second input MOD and the second output R, and generate a modulated pulse signal, and the ΣΔ noise-shaping unit is configured to receive the first output and the modulated pulse signal, and generate a sequence whose average equals approximately the first input over the second input.

摘要翻译： 根据本发明的用于分数N频率合成器的可变模量Σ-Δ调制器（＆Sgr＆amp; Dgr））可以包括整数除法单元; 脉冲宽度调制（PWM）发生器，＆Sgr＆amp; Dgr; 噪声整形单元，用于接收第一可编程整数的第一输入FRAC和用于接收第二输入的第二输入MOD，其中所述整数除法单元被配置为执行从所述第一输入和所述第二输入到第一输出的转换 FRAC'和第二输出R，PWM发生器被配置为接收第二输入MOD和第二输出R，并产生调制脉冲信号，并且＆S＆amp; Dgr; 噪声整形单元被配置为接收第一输出和调制脉冲信号，并且生成其平均值等于第二输入上的第一输入的序列。

公开(公告)号：US07043221B2

公开(公告)日：2006-05-09

申请号：US10486624

申请日：2002-07-19

申请人： Fabrice Jovenin ,  David Canard

发明人： Fabrice Jovenin ,  David Canard

IPC分类号： H04B1/10

CPC分类号： H03B21/02 ,  H03D7/18

摘要： A mixer circuit with image frequency rejection comprising a quadrature phase divider (30, 30′) presenting an input connected to the input (Fi) of the mixer circuit and two outputs respectively delivering two signals in phase quadrature which are applied respectively to two simple mixers (31, 32; 31′, 32′), said mixer circuit comprising a quadrature phase and frequency divider (33, 33′) having a frequency division ratio and presenting two inputs respectively connected to the respective outputs of the two simple mixers (31, 32; 31′, 32′) and a first output delivering a first output signal (Fo) of the mixer circuit, which signal is applied to the inputs of the two simple mixers.

摘要翻译： 一种具有图像频率抑制的混频器电路，包括正交相位分配器（30,30'），其呈现连接到混频器电路的输入端（F SUB）的输入端和两个输出端，分别传送相位正交的两个信号 它们分别应用于两个简单混合器（31,32; 31'，32'），所述混频器电路包括具有分频比的正交相位和分频器（33,33'），并且呈现分别连接到相应 两个简单混合器（31,32; 31'，32'）的输出和第一输出端输出混频器电路的第一输出信号（F SUB），该信号被施加到 两个简单的混音器。

公开(公告)号：US20140218009A1

公开(公告)日：2014-08-07

申请号：US14241186

申请日：2011-08-29

申请人： David Canard ,  Matthieu Lecuyer

发明人： David Canard ,  Matthieu Lecuyer

IPC分类号： G01R22/00

CPC分类号： G01R22/00 ,  G01R29/023 ,  G04F10/005 ,  H03K3/0322

摘要： A device for measuring a duration of a level of an electrical signal, comprising first ring oscillator comprising inverting gates, whose electrical power supply is modulated by the electrical signal; second ring oscillator whose electrical power supply is not modulated by the electrical signal; first counting unit configured to count a total number of gate-to-gate transitions of a point of instability of the first ring oscillator, a point of instability being present at an inverting gate when a logic level at an input to the inverting gate is equal to a logic level at an output from the inverting gate; second counting unit configured to count a total number of gate-to-gate transitions of a point of instability of the second ring oscillator; and determining unit configured to determine a duration of a level of the electrical signal on a basis of values of the first and second counting units.

摘要翻译： 一种用于测量电信号电平持续时间的装置，包括第一环形振荡器，其包括反相门，其电源由电信号调制; 第二环形振荡器，其电源不被电信号调制; 第一计数单元，被配置为对第一环形振荡器的不稳定点的门到门转换的总数进行计数，当反相门的输入端的逻辑电平相等时，不稳定点存在于反相门 在反相门的输出处为逻辑电平; 第二计数单元，被配置为对第二环形振荡器的不稳定点的门到门转换的总数进行计数; 以及确定单元，被配置为基于所述第一和第二计数单元的值来确定所述电信号的电平的持续时间。

公开(公告)号：US07038496B2

公开(公告)日：2006-05-02

申请号：US09995470

申请日：2001-11-28

申请人： David Canard ,  Vincent Fillatre

发明人： David Canard ,  Vincent Fillatre

IPC分类号： G01R23/02

CPC分类号： H03J5/0272 ,  H03D13/003 ,  H03L7/085 ,  H03L7/0891

摘要： The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a phase/frequency comparator PD, which supplies a regulation signal Tun, which is subjected to pulse width modulation according to the difference observed. The device also includes a current source, which is designed to emit a charge current Ics, with a value which is controlled by the regulation signal Tun. The device further includes a capacitive element Cs, which is designed to generate the control signal Vcnt, under the effect of the charge current Ics. By means of a regulation signal Tun, which has a frequency which is virtually constant, the invention makes it possible to impose high-frequency variations on the control signal Vcnt.

摘要翻译： 本发明涉及用于比较CMP的器件，其被设计为发射表示存在于输入信号频率Vdiv和Vref之间的差的控制信号Vcnt。 根据本发明的装置包括相位/频率比较器PD，该相位/频率比较器PD提供调节信号Tun，该调节信号Tun根据观测到的差异进行脉冲宽度调制。 该装置还包括电流源，其被设计为发射具有由调节信号Tun控制的值的充电电流Ics。 该装置还包括在充电电流Ics的作用下设计成产生控制信号Vcnt的电容元件Cs。 通过具有几乎恒定的频率的调节信号Tun，本发明使得可以对控制信号Vcnt施加高频变化。

公开(公告)号：US6163182A

公开(公告)日：2000-12-19

申请号：US060089

申请日：1998-04-14

申请人： David Canard ,  Vincent Fillatre

发明人： David Canard ,  Vincent Fillatre

IPC分类号： H03L7/183 ,  H03J5/02 ,  H03K3/286 ,  H03K23/54 ,  H03K23/64 ,  H04B1/26 ,  H03K21/00

CPC分类号： H03J5/0272 ,  H03K23/542

摘要： A frequency divider DIV/4 composed of memory cells (DL1 . . . DL4) realized in ECL technology, whose data paths constitute a loop, the data output Q4 of the last memory cell DL4 being cross-connected to the data input D1 of the first memory cell DL1. The clock inputs Ck of the memory cells DL1, DL3 of the odd rank are connected to the input IN of the frequency divider circuit DIV/4, while the others are cross-connected to said input. Such a frequency divider generates a noise having a unique frequency which is twice the frequency of the input signal, irrespective of the division ratio obtained.

摘要翻译： 由ECL技术实现的存储单元（DL1 ... DL4）组成的分频器DIV / 4，其数据路径构成一个环路，最后一个存储单元DL4的数据输出端Q4交叉连接到数据输入端 第一存储单元DL1。 奇数级的存储单元DL1，DL3的时钟输入Ck连接到分频器电路DIV / 4的输入IN，而其它的与交叉连接到所述输入。 这种分频器产生具有独特频率的噪声，该频率是输入信号频率的两倍，而与获得的分频比无关。

公开(公告)号：US06407643B2

公开(公告)日：2002-06-18

申请号：US09801627

申请日：2001-03-08

申请人： David Canard ,  Vincent Fillatre

发明人： David Canard ,  Vincent Fillatre

IPC分类号： H03L706

CPC分类号： H03L7/1976 ,  H03L7/081 ,  H03L7/0893

摘要： The invention relates to a phase-locked loop, comprising: an oscillator OSC intended to produce an output signal Vlo, a frequency divider DIV intended to receive the output signal Vlo from the oscillator OSC, and a phase/frequency detector PD intended to compare the frequency FDIV of the output signal Vdiv of the divider DIV with the frequency of a comparison signal Vcomp, and to supply a tuning signal Vtun to the oscillator, which tuning signal defines the oscillation frequency of the oscillator, A phase-locked loop in accordance with the invention is provided with correction means PMOD intended to detect a parasitic phase modulation applied to the output signal Vlo of the oscillator OSC, and to apply a phase modulation, which is similar to said parasitic phase modulation, to the comparison signal Vcomp. The invention enables a fractional-N frequency divider to be used and hence the noise generated by the loop to be limited, without affecting the spectral purity of the output signal Vlo of the oscillator OSC. Application: Tuners for receivers of television and radiotelephone signals.

摘要翻译： 本发明涉及一种锁相环，包括：用于产生输出信号Vlo的振荡器OSC，用于从振荡器OSC接收输出信号Vlo的分频器DIV，以及用于将频率比较的相位/频率检测器 FDIV的分频器DIV的输出信号Vdiv与比较信号Vcomp的频率相加，并将调谐信号Vtun提供给振荡器，该调谐信号定义振荡器的振荡频率，A锁相环根据 本发明提供了用于检测施加到振荡器OSC的输出信号Vlo的寄生相位调制的校正装置PMOD，并且将与所述寄生相位调制类似的相位调制施加到比较信号Vcomp。本发明使得 要使用的分数N分频器，因此由环路产生的噪声被限制，而不影响输出信号Vlo的频谱纯度 振荡器OSC。 应用：电视和无线电话信号接收机的调谐器。

公开(公告)号：US6150806A

公开(公告)日：2000-11-21

申请号：US376862

申请日：1999-08-18

申请人： David Canard ,  Vincent Fillatre

发明人： David Canard ,  Vincent Fillatre

IPC分类号： G05F3/26 ,  G05F3/20 ,  G05F3/22 ,  H02M3/07 ,  H03L7/093 ,  G05F1/565

CPC分类号： G05F3/20

摘要： A controlled current source is disclosed which receives a control signal and supplies a current at an output. The current source includes a power module having a plurality of parallel-arranged power transistors, whose collectors are jointly connected to the output of the current source, a control module to receive the control signal, and an output to supply a signal enabling the power transistors to be turned on, wherein, the emitters of the power transistors are jointly connected to the output of the control module, the output for supplying a current whose value depends on the value of the control signal, the bases of the power transistors being permanently subjected to a voltage of a predetermined value enabling the power transistors to be rendered potentially conducting. By pre-charging the parasitic capacitances of the power transistors, the transistors are turned on at an accelerated rate.

摘要翻译： 公开了一种控制电流源，其接收控制信号并在输出端提供电流。 电流源包括具有多个并联布置的功率晶体管的功率模块，其集电极共同连接到电流源的输出端，用于接收控制信号的控制模块和用于提供功率晶体管的信号的输出 导通，其中，功率晶体管的发射极共同连接到控制模块的输出，用于提供其值取决于控制信号的值的电流的输出，功率晶体管的基极被永久地承受 达到使得功率晶体管能够潜在导通的预定值的电压。 通过对功率晶体管的寄生电容进行预充电，晶体管以加速的速率被导通。

公开(公告)号：US08928417B2

公开(公告)日：2015-01-06

申请号：US13465556

申请日：2012-05-07

申请人： David Canard

发明人： David Canard

IPC分类号： H03L7/00 ,  H03L7/085 ,  H03L7/089

CPC分类号： H03L7/085 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/1976

摘要： A phase frequency detector realizes a highly linear conversion from noise-shaped ΣΔ modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL.

摘要翻译： 相位频率检测器实现了从噪声形状＆Sgr;＆Dgr的高度线性转换; 调制成电荷量而不降低锁相环（PLL）相位噪声。 相位频率检测器可以具有Up信号输出和Down信号输出的结构，其中当分频VCO输入上升时Up信号上升，当分频VCO输入下降时Up信号下降，当分频VCO输入下降时Up信号上升 VCO输入上升，当参考输入上升时下降信号下降。 模式选择输入可用于快速锁定PLL。