公开(公告)号：US08343846B2

公开(公告)日：2013-01-01

申请号：US12131229

申请日：2008-06-02

申请人： Cha Deok Dong

发明人： Cha Deok Dong

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76232

摘要： A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including the first insulating layer; etching the second insulating layer to increase an aspect ratio on the isolation region; and forming a third insulating layer on a peripheral region of the second insulating layer to fill moats formed on the second insulating layer with the third insulating layer.

摘要翻译： 一种在半导体器件中形成隔离层的方法，包括：利用隔离掩模通过蚀刻在半导体衬底的隔离区上形成沟槽; 在沟槽的下部形成第一绝缘层; 在包括第一绝缘层的半导体衬底上形成第二绝缘层; 蚀刻第二绝缘层以增加隔离区上的纵横比; 以及在所述第二绝缘层的周边区域上形成第三绝缘层，以用所述第三绝缘层填充形成在所述第二绝缘层上的护城河。

公开(公告)号：US08288263B2

公开(公告)日：2012-10-16

申请号：US12850903

申请日：2010-08-05

申请人： Gyu-Hyun Kim ,  Kwon Hong ,  Cha-Deok Dong

发明人： Gyu-Hyun Kim ,  Kwon Hong ,  Cha-Deok Dong

IPC分类号： H01L21/28

CPC分类号： H01L28/60 ,  H01L21/02057 ,  H01L27/10852 ,  H01L27/11519 ,  H01L27/11524

摘要： A method for fabricating a semiconductor device includes forming a multilayer, forming a plurality of patterns by etching the multilayer and a portion of the substrate, forming a supporter to support the plurality of patterns, and removing residues formed during the etching.

摘要翻译： 一种制造半导体器件的方法包括：通过蚀刻多层和一部分衬底形成多个图案，形成多个图案，形成支撑体以支撑多个图案，以及去除蚀刻期间形成的残留物。

公开(公告)号：US07932159B2

公开(公告)日：2011-04-26

申请号：US12943578

申请日：2010-11-10

申请人： Cha Deok Dong

发明人： Cha Deok Dong

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers.

摘要翻译： 闪存器件及其制造方法技术领域本发明涉及闪速存储器件及其制造方法。 在本发明的一个方面，闪存器件包括形成在半导体衬底中并且在其下部具有台阶的沟槽，形成在半导体衬底的有源区中的隧道绝缘层，形成在隧道绝缘层上的第一导电层 沟槽和第一导电层之间的隔离层间隙填充，以及形成在第一导电层上并具有与隔离层部分重叠的一侧的第二导电层。

公开(公告)号：US20090170282A1

公开(公告)日：2009-07-02

申请号：US12131229

申请日：2008-06-02

申请人： Cha Deok Dong

发明人： Cha Deok Dong

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/76232

摘要： A method of forming isolation layer in a semiconductor device, comprising forming a trench on an isolation region of a semiconductor substrate by etching utilizing an isolation mask; forming a first insulating layer on a lower portion of the trench; forming a second insulating layer on the semiconductor substrate including the first insulating layer; etching the second insulating layer to increase an aspect ratio on the isolation region; and forming a third insulating layer on a peripheral region of the second insulating layer to fill moats formed on the second insulating layer with the third insulating layer.

摘要翻译： 一种在半导体器件中形成隔离层的方法，包括：利用隔离掩模通过蚀刻在半导体衬底的隔离区上形成沟槽; 在沟槽的下部形成第一绝缘层; 在包括第一绝缘层的半导体衬底上形成第二绝缘层; 蚀刻第二绝缘层以增加隔离区上的纵横比; 以及在所述第二绝缘层的周边区域上形成第三绝缘层，以用所述第三绝缘层填充形成在所述第二绝缘层上的护城河。

公开(公告)号：US20080277665A1

公开(公告)日：2008-11-13

申请号：US11967199

申请日：2007-12-30

申请人： Cha-Deok DONG ,  Il-Seok Seo

发明人： Cha-Deok DONG ,  Il-Seok Seo

IPC分类号： H01L21/36 ,  H01L29/04 ,  H01L29/788

CPC分类号： H01L29/7883 ,  H01L29/40114 ,  H01L29/42324

摘要： A semiconductor device includes a conductive layer including a first and a second polysilicon layers having different grain boundaries, wherein a portion or an entire region of the first polysilicon layer is crystallized and wherein a grain boundary in a crystallized region is bigger than the grain boundary of the second polysilicon layer.

摘要翻译： 半导体器件包括具有不同晶界的第一多晶硅层和第二多晶硅层的导电层，其中第一多晶硅层的一部分或整个区域结晶，其中结晶区域中的晶界大于晶界的晶界 第二多晶硅层。

公开(公告)号：US06900096B2

公开(公告)日：2005-05-31

申请号：US10285590

申请日：2002-11-01

申请人： Cha Deok Dong ,  Sang Wook Park

发明人： Cha Deok Dong ,  Sang Wook Park

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28273

摘要： The present invention relates to a method of manufacturing a flash memory cell capable of preventing an oxidation of a dielectric film between a floating gate and a control gate, in a manner that a polysilicon film for floating gate is deposited, nitrogen ions are injected to make amorphous and contaminate the surface of the polysilicon film.

摘要翻译： 本发明涉及一种制造闪存单元的方法，该闪速存储单元能够防止浮置栅极和控制栅极之间的电介质膜氧化，从而沉积浮栅的多晶硅膜，注入氮离子以形成 无定形并污染多晶硅膜的表面。

公开(公告)号：US06849519B2

公开(公告)日：2005-02-01

申请号：US10611500

申请日：2003-07-01

申请人： Cha Deok Dong

发明人： Cha Deok Dong

IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L21/762

CPC分类号： H01L21/76213 ,  H01L21/76205 ,  H01L21/76235

摘要： A method of forming an isolation layer in semiconductor devices is disclosed. The method includes forming the isolating film by means of a method in which a method of forming a V-type trench at the isolation region, implanting ions capable of accelerating oxidization action into the center portion of the V-type trench, implementing an oxidization process to form an insulating film consisting of an oxide film at the isolation region, and then completely burying the trench with an insulating material, using the LOCOS method, and a method of forming a trench type isolation layer, are applied together. Therefore, as the top corner of the trench is formed with an inclination, and a concentration of the electric field and a formation of a moat can be simultaneously prevented.

摘要翻译： 公开了一种在半导体器件中形成隔离层的方法。 该方法包括通过以下方法形成隔离膜：其中在隔离区域形成V型沟槽的方法，将能够加速氧化作用的离子注入到V型沟槽的中心部分中，实现氧化过程 在隔离区域形成由氧化物膜构成的绝缘膜，然后使用LOCOS方法和形成沟槽型隔离层的方法将绝缘材料完全埋入沟槽中。 因此，由于沟槽的顶角形成倾斜，并且可以同时防止电场的集中和护城河的形成。

公开(公告)号：US06777348B2

公开(公告)日：2004-08-17

申请号：US10631362

申请日：2003-07-31

申请人： Seung Woo Shin ,  Cha Deok Dong

发明人： Seung Woo Shin ,  Cha Deok Dong

IPC分类号： H01L2131

CPC分类号： H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31662

摘要： Disclosed is a method of forming an oxynitride film. The method comprises the steps of loading a silicon substrate into an oxidization furnace, implanting an oxygen based source gas into the oxidization furnace to grow a pure silicon oxide film on the silicon substrate, blocking implantation of the oxygen based source gas and implanting an inert gas to exhaust the oxygen based source gas remaining within the oxidization furnace, raising a temperature within the oxidization furnace to a nitrification process temperature, stabilizing the temperature within the oxidization furnace, implementing a nitrification process for the pure silicon oxide film by implanting a nitrogen based source gas, and stopping implantation of the nitrogen based source gas and rapidly cooling the oxidization furnace while implanting the inert gas into the oxidization furnace.

摘要翻译： 公开了形成氮氧化物膜的方法。 该方法包括以下步骤：将硅衬底装载到氧化炉中，将氧基源气体注入到氧化炉中以在硅衬底上生长纯氧化硅膜，阻止氧基源气体的注入和注入惰性气体 排出残留在氧化炉内的氧气源气体，将氧化炉内的温度升高至硝化处理温度，稳定氧化炉内的温度，通过注入氮源，实施纯氧化硅膜的硝化处理 气体，并停止氮源气体的注入，并在将惰性气体注入氧化炉的同时快速冷却氧化炉。

公开(公告)号：US08470673B2

公开(公告)日：2013-06-25

申请号：US12841845

申请日：2010-07-22

申请人： Cha-Deok Dong ,  Gyu-Hyun Kim

发明人： Cha-Deok Dong ,  Gyu-Hyun Kim

IPC分类号： H01L21/8239

CPC分类号： H01L29/78 ,  H01L21/743 ,  H01L27/10876 ,  H01L27/10885

摘要： A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction.

摘要翻译： 半导体器件包括具有侧壁的有源区，其具有侧壁台阶，形成在侧壁台阶的表面下方的结以及被配置为接触接合部的掩埋位线。

公开(公告)号：US08426280B2

公开(公告)日：2013-04-23

申请号：US13448046

申请日：2012-04-16

申请人： Cha-Deok Dong

发明人： Cha-Deok Dong

IPC分类号： H01L21/336

CPC分类号： H01L29/401 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792

摘要： There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer.

摘要翻译： 提供了一种电荷阱型非易失性存储器件及其制造方法，该电荷阱型非易失性存储器件包括：在衬底上形成的隧道绝缘层; 形成在隧道绝缘层上的电荷陷阱层，电荷陷阱层包括电荷陷阱多晶硅薄层和电荷陷阱氮化物基层; 形成在电荷陷阱层上的电荷阻挡层; 形成在电荷阻挡层上的栅电极; 以及形成在电荷陷阱层的侧壁上的氧化物基间隔物，并且被提供以隔离电荷陷阱层。