公开(公告)号：US06506661B1

公开(公告)日：2003-01-14

申请号：US09541482

申请日：2000-04-03

申请人： Chai-Der Chang ,  Pin-Hsiang Chin

发明人： Chai-Der Chang ,  Pin-Hsiang Chin

IPC分类号： H01L2176

CPC分类号： B60C11/0309 ,  B60C11/1353 ,  B60C2011/1361

摘要： In accordance with the objectives of the invention a new method is provided for the definition and delineation of active regions in the surface of a semiconductor substrate. A layer of pad oxide is grown on the surface of the substrate, the layer of pad oxide is patterned and etched whereby the pad oxide remains in place over areas where the isolation regions are to be created. The underlying silicon substrate is in this manner exposed; the regions of the silicon substrate that are exposed are the regions of the substrate where active devices are to be created. The exposed surface of the substrate is cleaned; the openings in the layer of pad oxide are selectively filled with a deposition of epitaxial silicon. The created structure is heat treated to improve the interface between the patterned and etched layer of pad oxide and the deposited epitaxial silicon. The created pattern of pad oxide can now be used as regions of field isolation over the surface of the substrate.

摘要翻译： 根据本发明的目的，提供了一种用于定义和描绘半导体衬底的表面中的有源区的新方法。 在衬底的表面上生长衬垫氧化物层，对衬垫氧化物层进行图案化和蚀刻，由此衬垫氧化物在要产生隔离区域的区域保持在适当位置。 下面的硅衬底以这种方式暴露; 被暴露的硅衬底的区域是要产生有源器件的衬底的区域。 清洁基板的暴露表面; 衬垫氧化物层中的开口被选择性地填充外延硅的沉积。 所产生的结构被热处理以改善衬垫氧化物的图案化和蚀刻层与沉积的外延硅之间的界面。 所形成的衬垫氧化物图案现在可以用作衬底表面上的场隔离区域。

公开(公告)号：US06346366B1

公开(公告)日：2002-02-12

申请号：US09596906

申请日：2000-06-19

申请人： Tsu-Yu Chu ,  Yi-Tung Yen ,  Chai-Der Chang

发明人： Tsu-Yu Chu ,  Yi-Tung Yen ,  Chai-Der Chang

IPC分类号： G03C500

CPC分类号： H01L21/765 ,  H01L27/10873 ,  H01L27/10894

摘要： A method for making advanced guard rings in a stacked film on logic/merged DRAM circuits using a novel mask design is achieved. After forming a patterned amorphous silicon (a-Si) layer that has blanket portions over the logic region, a stacked film is deposited over the a-Si layer and extending over the edge and on the memory region. A first photoresist etch mask is used to pattern FET gate electrodes in the stacked film, and the etch mask includes a portion having a minimum width W over the edge of the a-Si layer to form a wide guard ring. This wide guard ring replaces a narrow guard ring that inadvertently forms during conventional processing and that is susceptible to peeling and particle contamination of the wafer. A second photoresist etch mask is used to pattern the a-Si layer to form FET gate electrodes over the logic region. The remaining process steps commonly practiced in the industry are carried out to complete the logic/merged DRAM circuit without the peeling and contamination that results from a narrow guard ring.

摘要翻译： 实现了使用新颖的掩模设计在逻辑/合并的DRAM电路上在堆叠膜中制造高级保护环的方法。 在形成在逻辑区域上具有覆盖部分的图案化非晶硅（a-Si）层之后，堆叠的膜沉积在a-Si层上并在边缘和存储区上延伸。 使用第一光致抗蚀剂蚀刻掩模来对层叠膜中的FET栅电极进行图案化，并且蚀刻掩模包括在a-Si层的边缘上具有最小宽度W的部分以形成宽的保护环。 这种宽保护环代替了常规加工过程中无意中形成的狭窄保护环，并且易受到晶片剥落和颗粒污染。 使用第二光致抗蚀剂蚀刻掩模来图案化a-Si层以在逻辑区域上形成FET栅电极。 执行在工业中通常实施的其余工艺步骤来完成逻辑/合并的DRAM电路，而不会由窄的保护环产生的剥离和污染。

公开(公告)号：US06242331B1

公开(公告)日：2001-06-05

申请号：US09467129

申请日：1999-12-20

申请人： Cheng-Yu Chu ,  Te-Fu Tseng ,  Chai-Der Chang ,  Chi-Hung Liao

发明人： Cheng-Yu Chu ,  Te-Fu Tseng ,  Chai-Der Chang ,  Chi-Hung Liao

IPC分类号： H01L213205

CPC分类号： H01L21/76804 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76814

摘要： A method for developing a semiconductor device low resistance electrical contact is described. In this process a gate oxide layer followed by a polysilicon layer is deposited on the semiconductor substrate in proximity to the device contact area. It is subsequently patterned with photoresist and etched to produce the desired gate structure. This is followed by a deposited layer of silicon dioxide or silicon nitride (SIN) which is appropriately patterned and etched to form gate isolation spacers. Then a nominal 300 Å layer of silicon nitride (SIN) is deposited followed by a layer of tetraethyl orthosilicate (TEOS) or borophosphosilicate glass (BPSG). The contact area is defined by photolithography, and the passivation layers are etched either by a dry etch such as a RIE process, or a combination of a wet BOE process followed by a dry etch, to form the metal contact holes. Prior to sputtering the contact metal, the contact area is cleaned with a 30 second dip in a BOE solution, followed by a Hydrogen Peroxide (H2O2) dip. This H2O2 cleaning step enables lower device contact resistance for the P+ contact areas.

摘要翻译： 描述了一种用于开发半导体器件低电阻电接触的方法。 在该过程中，在半导体衬底上沉积接近器件接触区的栅极氧化层，随后是多晶硅层。 随后用光致抗蚀剂图案化并蚀刻以产生所需的栅极结构。 之后是二氧化硅或氮化硅（SIN）的沉积层，其被适当地图案化和蚀刻以形成栅极隔离间隔物。 然后沉积标称的300Å氮化硅层（SIN），然后沉积原硅酸四乙酯（TEOS）或硼磷硅酸盐玻璃（BPSG）。 通过光刻法定义接触区域，并且通过诸如RIE工艺的干法蚀刻或者湿法BOE工艺的组合然后进行干蚀刻蚀刻钝化层，以形成金属接触孔。 在溅射接触金属之前，接触面积在BOE溶液中用30秒浸渍，然后用过氧化氢（H 2 O 2）浸渍进行清洗。 该H 2 O 2清洁步骤可以降低P +接触区域的器件接触电阻。

公开(公告)号：US06682659B1

公开(公告)日：2004-01-27

申请号：US09435669

申请日：1999-11-08

申请人： Ching-Wen Cho ,  Kuwi-Jen Chang ,  Sen-Fu Chen ,  Kuang-Peng Lin ,  Shing-Jzy Tay ,  Szu-Hung Yang ,  Chai-Der Chang ,  Kuo-Su Huang ,  Jen-Shiang Leu ,  Weng-Liang Fang ,  Jyh-Ping Wang ,  Jow-Feng Lee

发明人： Ching-Wen Cho ,  Kuwi-Jen Chang ,  Sen-Fu Chen ,  Kuang-Peng Lin ,  Shing-Jzy Tay ,  Szu-Hung Yang ,  Chai-Der Chang ,  Kuo-Su Huang ,  Jen-Shiang Leu ,  Weng-Liang Fang ,  Jyh-Ping Wang ,  Jow-Feng Lee

IPC分类号： H01L21311

CPC分类号： H01L21/76838 ,  H01L21/02071 ,  H01L21/31116 ,  H01L21/321 ,  H01L21/76802 ,  H01L21/76883 ,  H01L21/76888

摘要： A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further processing of the substrate. There is then treated, while employing a first plasma method employing a first plasma gas composition comprising an oxidizing gas, the target layer to form an oxidized target layer having an inhibited susceptibility to corrosion incident to contact with the corrosive material employed for further processing of the substrate. Finally, there is then processed further, while employing the corrosive material, the substrate. The method is useful when forming bond pads within microelectronic fabrications. When directed towards forming patterned conductor layers, such as bond pads, the method optionally employs an inert plasma treatment of a patterned conductor layer followed by an aqueous ethanolamine treatment of the patterned conductor layer prior to a first plasma treatment of the patterned conductor layer.

摘要翻译： 一种钝化目标层的方法。 首先提供基板。 然后在基底上形成目标层，其中目标层容易受到与用于进一步处理基底的腐蚀性材料接触的腐蚀。 然后在使用采用包含氧化性气体的第一等离子体气体组合物的第一等离子体方法的同时，使用目标层形成被腐蚀的腐蚀敏感性的氧化目标层，以与用于进一步处理的腐蚀性材料接触 基质。 最后，在使用腐蚀性材料的同时，进一步处理基板。 当在微电子制造中形成接合焊盘时，该方法是有用的。 当指向形成图案化的导体层（例如接合焊盘）时，该方法可以在图案化的导体层的第一等离子体处理之前，任意地使用图案化导体层的惰性等离子体处理，然后进行图案化导体层的乙醇胺水溶液处理。