公开(公告)号：US06627475B1

公开(公告)日：2003-09-30

申请号：US09483034

申请日：2000-01-18

申请人： Hua Yu Yang ,  Ching-Wen Cho ,  Chih-Heng Shen

发明人： Hua Yu Yang ,  Ching-Wen Cho ,  Chih-Heng Shen

IPC分类号： H01L2100

CPC分类号： H01L27/14689 ,  H01L27/14601 ,  H01L27/1463

摘要： A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provided, containing a p-type region. An n-type photodiode region is formed within the p-type region. A field oxide isolation region is then formed which extends beyond the p-type region and also covers the p-type region except for an active region and an overlap part of the n-type photodiode region. An n-channel MOSFET is fabricated in the active region with one of the source/drain regions of the MOSFET extending over the overlap part of the n-type photodiode region. A blanket transparent insulating layer is then deposited.

摘要翻译： 公开了一种形成图像传感器的方法。 提供了部分处理的半导体晶片，其包含p型区域。 在p型区域内形成n型光电二极管区域。 然后形成场氧化物隔离区，其延伸超出p型区域，并且还覆盖除了n型光电二极管区域的有源区域和重叠部分之外的p型区域。 在有源区中制造n沟道MOSFET，MOSFET的源/漏区中的一个在n型光电二极管区域的重叠部分上延伸。 然后沉积一层覆盖的透明绝缘层。

公开(公告)号：US06380030B1

公开(公告)日：2002-04-30

申请号：US09298448

申请日：1999-04-23

申请人： Sen-Fu Chen ,  Ching-Wen Cho ,  Huan-Wen Wang ,  Chih-Heng Shen

发明人： Sen-Fu Chen ,  Ching-Wen Cho ,  Huan-Wen Wang ,  Chih-Heng Shen

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

摘要翻译： 公开了一种在浮动栅极的下边缘和分裂栅极闪存单元的控制栅极之间形成可靠的氮化硅间隔物的方法。 这通过形成具有垂直侧壁的浮动栅极，在包括垂直侧壁的浮动栅极之上形成高温氧化物层，随后是氮化硅层，离子注入氮化物层，然后选择性地蚀刻以形成稳定的氮化硅间隔物 定义明确的矩形。

公开(公告)号：US06624466B2

公开(公告)日：2003-09-23

申请号：US10074972

申请日：2002-02-12

申请人： Sen-Fu Chen ,  Ching-Wen Cho ,  Huan-Wen Wang ,  Chih-Heng Shen

发明人： Sen-Fu Chen ,  Ching-Wen Cho ,  Huan-Wen Wang ,  Chih-Heng Shen

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

公开(公告)号：US6077776A

公开(公告)日：2000-06-20

申请号：US40434

申请日：1998-03-18

申请人： Ching-Wen Cho ,  Cheng-Fu Hsu ,  Sen-Fu Chen ,  Po-Tao Chu

发明人： Ching-Wen Cho ,  Cheng-Fu Hsu ,  Sen-Fu Chen ,  Po-Tao Chu

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/4763

CPC分类号： H01L21/28123 ,  H01L21/28035 ,  H01L21/3105 ,  Y10S438/906

摘要： A new method of removing impurities and moisture from the surface of a wafer and thereby preventing polysilicon residue is described. A dielectric layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer. A hard mask layer is deposited overlying the polysilicon layer and patterned to form a hard mask. The wafer is cleaned whereby moisture and impurities form on the surfaces of the hard mask and the polysilicon layer. Thereafter, the wafer is heat treated whereby the moisture and impurities are removed. Thereafter, the polysilicon layer is etched away where it is not covered by the hard mask to complete formation of a polysilicon line on a wafer in the fabrication of an integrated circuit.

摘要翻译： 描述了从晶片表面去除杂质和水分从而防止多晶硅残渣的新方法。 在半导体衬底的表面上设置电介质层。 沉积覆盖在电介质层上的多晶硅层。 沉积覆盖多晶硅层的硬掩模层并图案化以形成硬掩模。 清洁晶片，从而在硬掩模和多晶硅层的表面上形成水分和杂质。 此后，对晶片进行热处理，除去水分和杂质。 此后，多晶硅层被蚀刻掉，其中它不被硬掩模覆盖，以在集成电路的制造中在晶片上完成多晶硅线的形成。

公开(公告)号：US6071826A

公开(公告)日：2000-06-06

申请号：US249259

申请日：1999-02-12

申请人： Ching-Wen Cho ,  Hua-Yu Yang ,  Sen-Fu Chen ,  Chih-Heng Shen ,  Wen-Cheng Chien ,  Chang-Jen Wu ,  Chi-Hsin Lo ,  Hui-Chen Chu

发明人： Ching-Wen Cho ,  Hua-Yu Yang ,  Sen-Fu Chen ,  Chih-Heng Shen ,  Wen-Cheng Chien ,  Chang-Jen Wu ,  Chi-Hsin Lo ,  Hui-Chen Chu

IPC分类号： H01L21/336 ,  H01L27/146 ,  H01L21/00

CPC分类号： H01L29/6659 ,  H01L27/14601 ,  H01L27/14683

摘要： A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.

摘要翻译： 一种用于形成CMOS图像传感器间隔结构的方法。 在基板上形成多晶硅栅电极; 第一电介质的薄层沉积在栅电极和衬底的顶部的暴露表面上。 接下来，沉积第二层电介质，之后进行蚀刻以形成电极间隔物。 沉积的第二介电层用作蚀刻停止层并且防止对栅电极的间隔物之间​​的衬底表面的损坏。 一种替代方法是使用薄层层作为停止层，并且在这样做时，由白色像素问题引起的源/漏损坏。

公开(公告)号：US6006764A

公开(公告)日：1999-12-28

申请号：US789239

申请日：1997-01-28

申请人： Po-Tao Chu ,  Ching-Wen Cho ,  Chia-Hung Lai ,  Chih-Chien Hung

发明人： Po-Tao Chu ,  Ching-Wen Cho ,  Chia-Hung Lai ,  Chih-Chien Hung

IPC分类号： G03F7/42 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/60 ,  H01L21/302

CPC分类号： H01L24/05 ,  G03F7/427 ,  H01L21/31133 ,  H01L21/31138 ,  H01L24/03 ,  H01L24/11 ,  H01L21/02071 ,  H01L21/31116 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/19042

摘要： The present invention provides a method of removing photoresist from a wafer surface having a bonding pad using a three step clean composed of (1) a wet cleaning the substrate, (2) a F-containing gas high temperature plasma treatment which prevents the corrosion of aluminum contact pad, and (3) completely striping the photoresist strip using an O.sub.2 dry ash. The invention eliminates metal bonding pad corrosion and the completely removes residual photoresist from keyholes.

摘要翻译： 本发明提供一种从具有接合焊盘的晶片表面去除光致抗蚀剂的方法，该焊盘使用由（1）湿式清洗基板组成的三步清洁，（2）含F气体高温等离子体处理，其防止腐蚀 铝接触垫，和（3）使用O2干灰完全剥离光致抗蚀剂条。 本发明消除了金属焊盘腐蚀，并且彻底地从键槽中去除残留的光致抗蚀剂。

公开(公告)号：US06682659B1

公开(公告)日：2004-01-27

申请号：US09435669

申请日：1999-11-08

申请人： Ching-Wen Cho ,  Kuwi-Jen Chang ,  Sen-Fu Chen ,  Kuang-Peng Lin ,  Shing-Jzy Tay ,  Szu-Hung Yang ,  Chai-Der Chang ,  Kuo-Su Huang ,  Jen-Shiang Leu ,  Weng-Liang Fang ,  Jyh-Ping Wang ,  Jow-Feng Lee

发明人： Ching-Wen Cho ,  Kuwi-Jen Chang ,  Sen-Fu Chen ,  Kuang-Peng Lin ,  Shing-Jzy Tay ,  Szu-Hung Yang ,  Chai-Der Chang ,  Kuo-Su Huang ,  Jen-Shiang Leu ,  Weng-Liang Fang ,  Jyh-Ping Wang ,  Jow-Feng Lee

IPC分类号： H01L21311

CPC分类号： H01L21/76838 ,  H01L21/02071 ,  H01L21/31116 ,  H01L21/321 ,  H01L21/76802 ,  H01L21/76883 ,  H01L21/76888

摘要： A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further processing of the substrate. There is then treated, while employing a first plasma method employing a first plasma gas composition comprising an oxidizing gas, the target layer to form an oxidized target layer having an inhibited susceptibility to corrosion incident to contact with the corrosive material employed for further processing of the substrate. Finally, there is then processed further, while employing the corrosive material, the substrate. The method is useful when forming bond pads within microelectronic fabrications. When directed towards forming patterned conductor layers, such as bond pads, the method optionally employs an inert plasma treatment of a patterned conductor layer followed by an aqueous ethanolamine treatment of the patterned conductor layer prior to a first plasma treatment of the patterned conductor layer.

摘要翻译： 一种钝化目标层的方法。 首先提供基板。 然后在基底上形成目标层，其中目标层容易受到与用于进一步处理基底的腐蚀性材料接触的腐蚀。 然后在使用采用包含氧化性气体的第一等离子体气体组合物的第一等离子体方法的同时，使用目标层形成被腐蚀的腐蚀敏感性的氧化目标层，以与用于进一步处理的腐蚀性材料接触 基质。 最后，在使用腐蚀性材料的同时，进一步处理基板。 当在微电子制造中形成接合焊盘时，该方法是有用的。 当指向形成图案化的导体层（例如接合焊盘）时，该方法可以在图案化的导体层的第一等离子体处理之前，任意地使用图案化导体层的惰性等离子体处理，然后进行图案化导体层的乙醇胺水溶液处理。

公开(公告)号：US06660624B2

公开(公告)日：2003-12-09

申请号：US10076891

申请日：2002-02-14

申请人： Jiann-Tyng Tzeng ,  Jih-Ren Tsai ,  Michael Wu ,  Ching-Wen Cho

发明人： Jiann-Tyng Tzeng ,  Jih-Ren Tsai ,  Michael Wu ,  Ching-Wen Cho

IPC分类号： H01L2144

CPC分类号： H01L21/31116 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/31144 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

摘要： A method for reducing a fluorine contamination level on a semiconductor wafer process surface including providing a semiconductor wafer surface having a process surface including an uppermost polyimide containing layer; reactive ion etching the process surface to include exposure of the process surface to a hydrofluorocarbon containing plasma; and heating the process surface according to a temperature profile to reduce a fluorine contamination level.

摘要翻译： 一种用于降低半导体晶片工艺表面上的氟污染水平的方法，包括提供具有包括最上面的聚酰亚胺含有层的工艺表面的半导体晶片表面; 反应离子蚀刻工艺表面以包括将工艺表面暴露于含有氢氟烃的等离子体; 并根据温度曲线加热工艺表面以降低氟污染水平。

公开(公告)号：US06620683B1

公开(公告)日：2003-09-16

申请号：US10003841

申请日：2001-12-04

申请人： Boson Lin ,  Ching-Wen Cho ,  David Ho

发明人： Boson Lin ,  Ching-Wen Cho ,  David Ho

IPC分类号： H01L21336

CPC分类号： H01L21/28211 ,  H01L21/28167 ,  H01L27/115 ,  H01L27/11521

摘要： A semiconductor EEPROM device and a method for making it are achieved. The EEPROM device is a novel twin-bit cell structure with adjacent floating gates having a common control gate and common bit-line contact in each cell area. In each cell area a first and second floating gate is formed. Source areas are formed in the substrate adjacent to the outer edges of the floating gates and a drain area is formed between and adjacent to the floating gates. A gate oxide is formed over the floating gates. A control gate is formed over the drain area and patterned to also partially extend over the floating gates. The control gate is also patterned to provide a recess for a bit-line contact to the drain area. The recess results in reduced cell area and the non-critical overlay of the control gate over the floating gates results in relaxed overlay alignment.

摘要翻译： 实现半导体EEPROM器件及其制造方法。 EEPROM器件是一种新颖的双位单元结构，其中相邻浮置栅极具有在每个单元区域中的公共控制栅极和公共位线接触。 在每个单元区域中，形成第一和第二浮栅。 源极区域形成在与浮置栅极的外边缘相邻的衬底中，并且在浮栅之间形成漏极区。 在浮动栅极上形成栅极氧化物。 控制栅极形成在漏极区域上并且被图案化以在浮栅上也部分地延伸。 控制栅极也被图案化以提供用于与漏极区域的位线接触的凹部。 凹槽导致细胞区域减小，并且控制栅极在浮动栅极上的非关键覆盖导致松弛的覆盖对准。

公开(公告)号：US6157867A

公开(公告)日：2000-12-05

申请号：US31654

申请日：1998-02-27

申请人： Yuan-Ko Hwang ,  Ching-Wen Cho

发明人： Yuan-Ko Hwang ,  Ching-Wen Cho

IPC分类号： C23C14/54 ,  C23C16/52 ,  G05B23/02 ,  H01J37/32 ,  G06F19/00

CPC分类号： H01J37/32935 ,  C23C14/544 ,  C23C16/52 ,  G05B23/0235 ,  G05B23/0286 ,  G05B2219/24042

摘要： A method for operating a plasma processing system comprises the following steps. Produce a plasma in a plasma processing chamber operating upon a selected workpiece. Perform in situ detection of electromagnetic radiation of a certain wavelength generated in the plasma in the plasma processing chamber. Calculate a first intensity difference of the certain wavelength from a set point of intensity. Halt production of the plasma in the plasma processing chamber if the first intensity difference is outside of specifications.

摘要翻译： 一种操作等离子体处理系统的方法包括以下步骤。 在等离子体处理室中产生等离子体，其操作在所选择的工件上。 对等离子体处理室中的等离子体中产生的一定波长的电磁辐射进行原位检测。 计算一定波长与强度设定点的第一强度差。 如果第一强度差超出规格，则在等离子体处理室中停止生产等离子体。