公开(公告)号：US20070171991A1

公开(公告)日：2007-07-26

申请号：US11627379

申请日：2007-01-26

申请人： Hsien-Chun Chang ,  Chao-Hsin Lu ,  Ming-Yen Hsu

发明人： Hsien-Chun Chang ,  Chao-Hsin Lu ,  Ming-Yen Hsu

IPC分类号： H04L25/00

CPC分类号： H04L25/0272 ,  H03K19/017527 ,  H03K19/1732

摘要： A current-mode differential signal transmitting circuit is disclosed, including a transmitter having a first transmitting module and a second transmitting module. The first transmitting module includes a plurality of first outputting units to output first data and a clock outputting signal. The second transmitting module includes a plurality of second outputting units for outputting second data, and the first and second transmitting modules share this clock outputting unit.

摘要翻译： 公开了一种电流模式差分信号发射电路，包括具有第一发射模块和第二发射模块的发射机。 第一发送模块包括多个第一输出单元，用于输出第一数据和时钟输出信号。 第二发送模块包括用于输出第二数据的多个第二输出单元，第一和第二发送模块共享该时钟输出单元。

公开(公告)号：US07822162B2

公开(公告)日：2010-10-26

申请号：US11627379

申请日：2007-01-26

申请人： Hsien-Chun Chang ,  Chao-Hsin Lu ,  Ming-Yen Hsu

发明人： Hsien-Chun Chang ,  Chao-Hsin Lu ,  Ming-Yen Hsu

IPC分类号： H04L7/00 ,  H04B3/00 ,  H03F3/45

CPC分类号： H04L25/0272 ,  H03K19/017527 ,  H03K19/1732

摘要： A current-mode differential signal transmitting circuit is disclosed, including a transmitter having a first transmitting module and a second transmitting module. The first transmitting module includes a plurality of first outputting units to output first data and a clock outputting signal. The second transmitting module includes a plurality of second outputting units for outputting second data, and the first and second transmitting modules share this clock outputting unit.

摘要翻译： 公开了一种电流模式差分信号发射电路，包括具有第一发射模块和第二发射模块的发射机。 第一发送模块包括多个第一输出单元，用于输出第一数据和时钟输出信号。 第二发送模块包括用于输出第二数据的多个第二输出单元，第一和第二发送模块共享该时钟输出单元。

公开(公告)号：US08669896B2

公开(公告)日：2014-03-11

申请号：US13493999

申请日：2012-06-11

申请人： Jen-Che Tsai ,  Chao-Hsin Lu

发明人： Jen-Che Tsai ,  Chao-Hsin Lu

IPC分类号： H03M1/38

CPC分类号： H03M1/462

摘要： A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.

摘要翻译： 提供了一种控制连续比较寄存器模数转换器（SAR ADC）的方法。 基于该方法，SAR ADC接收控制SAR ADC转换速率的转换时钟。

公开(公告)号：US08290065B2

公开(公告)日：2012-10-16

申请号：US11878564

申请日：2007-07-25

申请人： Jui-Yuan Tsai ,  Chao-Hsin Lu

发明人： Jui-Yuan Tsai ,  Chao-Hsin Lu

IPC分类号： H04N7/12

CPC分类号： H04N5/0675

摘要： The invention discloses an image processing system comprising a video source system, a transmission medium, and a television system. The image processing systems of the video source system and the television system are equipped with an additional digital-to-analog converter and an additional analog-to-digital converter.

摘要翻译： 本发明公开了一种包括视频源系统，传输介质和电视系统的图像处理系统。 视频源系统和电视系统的图像处理系统配备有附加的数模转换器和附加的模拟 - 数字转换器。

公开(公告)号：US07933360B2

公开(公告)日：2011-04-26

申请号：US11162571

申请日：2005-09-15

申请人： Yu-Pin Chou ,  Chao-Hsin Lu ,  Hsu-Jung Tung

发明人： Yu-Pin Chou ,  Chao-Hsin Lu ,  Hsu-Jung Tung

IPC分类号： H03K9/00 ,  H04L27/00

CPC分类号： H04N17/004

摘要： A method to assess signal transmission quality and the adjust method thereof are proposed. First, different time points of a control signal at a receiving end are acquired and the number of signal transitions in a predetermined time interval is counted. Next, the number of signal transitions is recorded and compared to a reference value to obtain a comparison result. The quality of the control signal is then determined based on the comparison result. The parameter setting of the receiving end is adjusted according to the quality of the control signal received by the receiving end to get a better performance setting.

摘要翻译： 提出了一种评估信号传输质量的方法及其调整方法。 首先，获取接收端的控制信号的不同时间点，并对预定时间间隔内的信号转换次数进行计数。 接下来，记录信号转换的数量并将其与参考值进行比较以获得比较结果。 然后根据比较结果确定控制信号的质量。 根据接收端接收到的控制信号的质量调整接收端的参数设置，以获得更好的性能设置。

公开(公告)号：US07876142B2

公开(公告)日：2011-01-25

申请号：US11200209

申请日：2005-08-10

申请人： Chao-Hsin Lu

发明人： Chao-Hsin Lu

IPC分类号： H03K3/00

CPC分类号： H03K19/00323

摘要： A latch inverter includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first level-adjusting unit and a second level-adjusting unit. The first level-adjusting unit changes the voltage level of the source of the second PMOS transistor in advance, and the second level-adjusting unit changes the voltage level of the drain of the second NMOS transistor in advance.

摘要翻译： 锁存逆变器包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第一电平调整单元和第二电平调节单元。 第一电平调整单元预先改变第二PMOS晶体管的源极的电压电平，并且第二电平调整单元预先改变第二NMOS晶体管的漏极的电压电平。

公开(公告)号：US20130099953A1

公开(公告)日：2013-04-25

申请号：US13493999

申请日：2012-06-11

申请人： Jen-Che Tsai ,  Chao-Hsin Lu

发明人： Jen-Che Tsai ,  Chao-Hsin Lu

IPC分类号： H03M1/38

CPC分类号： H03M1/462

摘要： A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.

摘要翻译： 提供了一种控制连续比较寄存器模数转换器（SAR ADC）的方法。 基于该方法，SAR ADC接收控制SAR ADC转换速率的转换时钟。

公开(公告)号：US07778375B2

公开(公告)日：2010-08-17

申请号：US11246090

申请日：2005-10-11

申请人： Chao-Hsin Lu

发明人： Chao-Hsin Lu

IPC分类号： H03D3/24

CPC分类号： H03L7/0996 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/18 ,  H04L7/0338

摘要： A clock generator and a data recovery circuit. The clock generator includes a voltage control oscillator (VCO) for generating a sampling clock and multi-phase clocks, a multiplexer for receiving the multi-phase clocks and selecting one of the multi-phase clocks to generate a selected clock according to a selection signal, a phase-frequency detector for receiving the selected clock and a reference clock and generating a phase-frequency error signal, a charge pump and loop filter for receiving the phase-frequency error signal and generating a control voltage, a phase detector for receiving the sampling clock and an input signal and generating a phase error signal, and a digital low-pass filter for receiving the phase error signal and generating the selection signal. The digital low-pass filter clears an accumulated phase error when it generates the selection signal to force the multiplexer to change the phase.

摘要翻译： 时钟发生器和数据恢复电路。 时钟发生器包括用于产生采样时钟和多相时钟的压控振荡器（VCO），多路复用器，用于接收多相时钟并根据选择信号选择多相时钟之一以产生所选择的时钟 用于接收所选择的时钟和参考时钟并产生相位频率误差信号的相位频率检测器，用于接收相位频率误差信号并产生控制电压的电荷泵和环路滤波器，相位检测器，用于接收 采样时钟和输入信号并产生相位误差信号，以及数字低通滤波器，用于接收相位误差信号并产生选择信号。 当数字低通滤波器产生选择信号以使多路复用器改变相位时，会清除累积的相位误差。

公开(公告)号：US07453971B2

公开(公告)日：2008-11-18

申请号：US11865874

申请日：2007-10-02

申请人： Chao-Hsin Lu

发明人： Chao-Hsin Lu

IPC分类号： H04L7/00

CPC分类号： H03L7/093 ,  H03L7/0812 ,  H04L7/0331

摘要： A sampling-error phase compensating device and a method thereof for sequentially sampling data signals and outputting sampled data signals. The method sequentially includes: sampling each data signal according to a first sampling clock signal, and sequentially outputting corresponding phase detection signals according to the sampled data signals; sequentially outputting phase regulating signals, which correspond to the phase detection signals, respectively, according to the phase detection signals, wherein when the phase detection signals are the same, the phase regulating signals includes first-state phase regulating signals and second-state phase regulating signals, the first-state phase regulating signals correspond to the phase detection signals, and the number of the second-state phase regulating signals is smaller than that of the first-state phase regulating signals; and sequentially outputting second sampling clock signals according to the phase regulating signals, wherein phases of the sampling clock signals correspond to those of the phase regulating signals, respectively.

摘要翻译： 一种采样误差相位补偿装置及其方法，用于顺序采样数据信号并输出​​采样数据信号。 该方法依次包括：根据第一采样时钟信号对每个数据信号进行采样，并根据采样的数据信号顺序地输出相应的相位检测信号; 根据相位检测信号分别顺序地输出与相位检测信号相对应的相位调制信号，其中当相位检测信号相同时，相位调节信号包括第一状态相位调节信号和第二状态相位调节 信号，第一状态相位调节信号对应于相位检测信号，并且第二状态相位调节信号的数量小于第一状态相位调制信号的数量; 并且根据相位调节信号依次输出第二采样时钟信号，其中采样时钟信号的相位分别对应于相位调制信号的相位。

公开(公告)号：US20060220687A1

公开(公告)日：2006-10-05

申请号：US11277361

申请日：2006-03-24

申请人： Hung-Jen Chu ,  Chao-Hsin Lu ,  Shiu-Rong Tong ,  Yu-Pin Chou

发明人： Hung-Jen Chu ,  Chao-Hsin Lu ,  Shiu-Rong Tong ,  Yu-Pin Chou

IPC分类号： H03K19/00

CPC分类号： G06F1/22 ,  H03K19/1732

摘要： A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.

摘要翻译： 公开了一种具有可调节引脚排列功能的芯片。 芯片包括第一引脚，第二引脚，逻辑电路和选择电路。 逻辑电路包括第一端口和第二端口。 耦合到逻辑电路，第一引脚排列和第二引脚分布的选择电路控制第一引脚被耦合到第一端口或第二端口，并且控制第二引脚分布以耦合到第一端口或 第二个港口。