公开(公告)号：US20130099953A1

公开(公告)日：2013-04-25

申请号：US13493999

申请日：2012-06-11

申请人： Jen-Che Tsai ,  Chao-Hsin Lu

发明人： Jen-Che Tsai ,  Chao-Hsin Lu

IPC分类号： H03M1/38

CPC分类号： H03M1/462

摘要： A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.

摘要翻译： 提供了一种控制连续比较寄存器模数转换器（SAR ADC）的方法。 基于该方法，SAR ADC接收控制SAR ADC转换速率的转换时钟。

公开(公告)号：US20100066422A1

公开(公告)日：2010-03-18

申请号：US12479877

申请日：2009-06-08

申请人： Jen-Che Tsai

发明人： Jen-Che Tsai

IPC分类号： H03L7/00

CPC分类号： H03M3/354 ,  H03K5/133 ,  H03K2005/00097 ,  H03M3/458

摘要： A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a first clock signal according to a calibration control signal. The incoming reference clock has a predetermined phase and a predetermined frequency, The calibration control unit is for checking if the phase difference between the first clock signal and a second clock signal satisfies a predetermined criterion, and for adjusting the calibration control signal when the phase difference between the first clock signal and the second clock signal does not satisfy the predetermined criterion. The predetermined criterion is to check if the phase difference falls within a specific range associated with a clock period of one of the first clock signal and the second clock signal.

摘要翻译： 时钟定时校准电路包括时钟定时调整单元和校准控制单元。 时钟定时调整单元用于接收输入的参考时钟信号，并选择性地调整接收到的参考时钟信号，以根据校准控制信号产生第一时钟信号。 输入参考时钟具有预定相位和预定频率。校准控制单元用于检查第一时钟信号和第二时钟信号之间的相位差是否满足预定标准，并且当相位差 在第一时钟信号和第二时钟信号之间不满足预定标准。 预定标准是检查相位差是否落在与第一时钟信号和第二时钟信号之一的时钟周期相关联的特定范围内。

公开(公告)号：US20080137882A1

公开(公告)日：2008-06-12

申请号：US11949796

申请日：2007-12-04

申请人： Jen-Che Tsai ,  Yau Wai Wong

发明人： Jen-Che Tsai ,  Yau Wai Wong

IPC分类号： H04B15/00

CPC分类号： H03F1/305 ,  H03F3/187 ,  H03F2200/03 ,  H03F2200/465 ,  H03G3/348

摘要： An apparatus and a muting circuit. The apparatus comprises an amplifier, a mute circuit, a pull-down circuit, and a power detection circuit. The amplifier receives a power supply voltage and a common mode voltage, and amplifies an audio input signal to generate an audio output signal. The mute circuit, coupled to the amplifier, conducts the audio output signal to about ground level upon receiving a mute signal. The pull-down circuit, coupled to the amplifier, pulls the common mode voltage to about ground level upon receiving a pull-down signal. The power detection circuit, coupled to the mute circuit and the pull-down circuit, detects power-up or power-down of the power supply voltage, and generates the mute signal and a pull-down signal according to the power-up or power-down operation.

摘要翻译： 一种装置和静音电路。 该装置包括放大器，静音电路，下拉电路和功率检测电路。 放大器接收电源电压和共模电压，并放大音频输入信号以产生音频输出信号。 耦合到放大器的静音电路在接收到静音信号时将音频输出信号传导到大约地平面。 耦合到放大器的下拉电路在接收到下拉信号时将共模电压拉到大约接地电平。 耦合到静音电路和下拉电路的功率检测电路检测电源电压的上电或掉电，并根据上电或电源产生静音信号和下拉信号 下降操作。

公开(公告)号：US20080030389A1

公开(公告)日：2008-02-07

申请号：US11830041

申请日：2007-07-30

申请人： Jen-Che Tsai

发明人： Jen-Che Tsai

IPC分类号： H03M1/66 ,  H03M3/00

CPC分类号： H03M1/0682 ,  H03M1/804 ,  H03M3/464 ,  H03M3/502

摘要： A digital to analog converter including a first capacitor, a second capacitor, an operational amplifier, and a switch is disclosed. During a first period, the first capacitor stores a first voltage and the second capacitor stores a second voltage. The operational amplifier comprises an input and an output. The switch parallels the first and the second capacitors with the operational amplifier at the input and output according to a digital signal during a second period.

摘要翻译： 公开了一种包括第一电容器，第二电容器，运算放大器和开关的数模转换器。 在第一时段期间，第一电容器存储第一电压，第二电容器存储第二电压。 运算放大器包括输入和输出。 该开关在第二时段期间根据数字信号将运算放大器的第一和第二电容器与输入和输出相平行。

公开(公告)号：US08171335B2

公开(公告)日：2012-05-01

申请号：US12479877

申请日：2009-06-08

申请人： Jen-Che Tsai

发明人： Jen-Che Tsai

IPC分类号： G06F1/04

CPC分类号： H03M3/354 ,  H03K5/133 ,  H03K2005/00097 ,  H03M3/458

摘要： A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a first clock signal according to a calibration control signal. The incoming reference clock has a predetermined phase and a predetermined frequency, The calibration control unit is for checking if the phase difference between the first clock signal and a second clock signal satisfies a predetermined criterion, and for adjusting the calibration control signal when the phase difference between the first clock signal and the second clock signal does not satisfy the predetermined criterion. The predetermined criterion is to check if the phase difference falls within a specific range associated with a clock period of one of the first clock signal and the second clock signal.

摘要翻译： 时钟定时校准电路包括时钟定时调整单元和校准控制单元。 时钟定时调整单元用于接收输入的参考时钟信号，并选择性地调整接收到的参考时钟信号，以根据校准控制信号产生第一时钟信号。 输入参考时钟具有预定相位和预定频率。校准控制单元用于检查第一时钟信号和第二时钟信号之间的相位差是否满足预定标准，并且当相位差 在第一时钟信号和第二时钟信号之间不满足预定标准。 预定标准是检查相位差是否落在与第一时钟信号和第二时钟信号之一的时钟周期相关联的特定范围内。

公开(公告)号：US20110221618A1

公开(公告)日：2011-09-15

申请号：US12723680

申请日：2010-03-14

申请人： Jen-Che Tsai

发明人： Jen-Che Tsai

IPC分类号： H03M3/00

CPC分类号： H03M3/39

摘要： A continuous-time delta-sigma Analog to Digital Converter (ADC) with a compact structure comprises a loop filter, a summing circuit, a quantizer, and a current Digital to Analog Converter (DAC). The loop filter is utilized for receiving and noise-shaping an analog input signal, and accordingly outputting a positive and a negative loop voltages. The summing circuit comprises a positive and a negative summing resistors. The summing resistors are utilized for transforming a positive and negative feedback currents to be a positive and a negative feedback voltages, and summing the loop voltages and the feedback voltages so as to generate a positive and a negative summing voltages, respectively. The quantizer is utilized for outputting a digital output signal according to a difference between the positive and the negative summing voltages. The current DAC is utilized for generating the positive and the negative feedback currents according to the digital output signal.

摘要翻译： 具有紧凑结构的连续时间Δ-Σ模数转换器（ADC）包括环路滤波器，加法电路，量化器和当前的数模转换器（DAC）。 环路滤波器用于接收和噪声整形模拟输入信号，从而输出正和负的环路电压。 求和电路包括正和负相加电阻。 求和电阻用于将正和负反馈电流变换为正和负反馈电压，并将回路电压和反馈电压相加，以分别产生正和负相加电压。 量化器用于根据正和负求和电压之间的差异输出数字输出信号。 电流DAC用于根据数字输出信号产生正和负反馈电流。

公开(公告)号：US20090296950A1

公开(公告)日：2009-12-03

申请号：US12128607

申请日：2008-05-28

申请人： Sheng-Jui Huang ,  Yung-Yu Lin ,  Jen-Che Tsai ,  Tzueng-Yau Lin ,  Yau-Wai Wong ,  Chih-Horng Weng ,  Chi-Hui Wang

发明人： Sheng-Jui Huang ,  Yung-Yu Lin ,  Jen-Che Tsai ,  Tzueng-Yau Lin ,  Yau-Wai Wong ,  Chih-Horng Weng ,  Chi-Hui Wang

IPC分类号： H03F3/217 ,  H04R1/10

CPC分类号： H04R3/00 ,  H04R2420/01

摘要： A signal processing system and related method are disclosed. The signal processing system includes a signal processing module, powered by a low supply voltage, for processing signals; and an interface module, coupled to the signal processing module, powered by a high supply voltage, for outputting signals generated from the signal processing module; wherein the interface module comprises a plurality of high-voltage functional blocks integrated therein, and each of the functional blocks is configured to perform a predetermined interface functionality. In this way, the bill-of-material (BOM) cost can be reduced.

摘要翻译： 公开了一种信号处理系统及相关方法。 信号处理系统包括由低电源供电的信号处理模块，用于处理信号; 以及接口模块，其耦合到由高电源电压供电的所述信号处理模块，用于输出从所述信号处理模块产生的信号; 其中所述接口模块包括集成在其中的多个高压功能块，并且每个所述功能块被配置为执行预定的接口功能。 通过这种方式，可以减少物料单（BOM）成本。

公开(公告)号：US06978338B2

公开(公告)日：2005-12-20

申请号：US10100758

申请日：2002-03-19

申请人： Hsin-Min Wang ,  Huan-Tang Hsieh ,  Chang-Lien Wu ,  Jen-Che Tsai

发明人： Hsin-Min Wang ,  Huan-Tang Hsieh ,  Chang-Lien Wu ,  Jen-Che Tsai

IPC分类号： G06F13/14 ,  G06F13/42 ,  G06F13/20

CPC分类号： G06F13/4221

摘要： The present invention discloses a PCI extended function interface and PCI device using such an interface. The PCI extended function interface is suitable for use in a PCI device comprising a master device and at least one slave device. The PCI extended function interface comprises at least one connecting port and a first circuit. The slave device is coupled to a corresponding connecting port and the PCI extended function interface transmits a control signal through the connecting port to control the operation of a corresponding slave device. The first circuit is used to determine the configuration space.

摘要翻译： 本发明公开了一种使用这种接口的PCI扩展功能接口和PCI设备。 PCI扩展功能接口适用于包括主设备和至少一个从设备的PCI设备。 PCI扩展功能接口包括至少一个连接端口和第一电路。 从设备耦合到对应的连接端口，PCI扩展功能接口通过连接端口发送控制信号，以控制对应的从设备的操作。 第一个电路用于确定配置空间。

公开(公告)号：US20110285562A1

公开(公告)日：2011-11-24

申请号：US13197756

申请日：2011-08-03

申请人： Jen-Che Tsai

发明人： Jen-Che Tsai

IPC分类号： H03M1/12

CPC分类号： H03M3/39

摘要： A continuous-time delta-sigma Analog to Digital Converter (ADC) includes: a loop filter, for receiving and noise-shaping an analog input signal, and outputting a first loop voltage; a first summing resistor, for transforming a first feedback current to be a first feedback voltage, and summing the first loop voltage and the first feedback voltage so as to generate a first summing voltage, wherein the first summing voltage is equal to a sum of the first loop voltage and the first feedback voltage; a quantizer, for outputting a digital output signal according to the first summing voltage; and a current Digital to Analog Converter (DAC), for generating the first feedback current according to the digital output signal.

摘要翻译： 连续时间Δ-Σ模数转换器（ADC）包括：环路滤波器，用于接收和噪声整形模拟输入信号，并输出第一回路电压; 第一求和电阻器，用于将第一反馈电流变换为第一反馈电压，并且对第一回路电压和第一反馈电压求和以产生第一求和电压，其中第一求和电压等于 第一回路电压和第一反馈电压; 量化器，用于根据第一求和电压输出数字输出信号; 和当前的数模转换器（DAC），用于根据数字输出信号产生第一反馈电流。

公开(公告)号：US08018365B1

公开(公告)日：2011-09-13

申请号：US12723680

申请日：2010-03-14

申请人： Jen-Che Tsai

发明人： Jen-Che Tsai

IPC分类号： H03M3/00

CPC分类号： H03M3/39

摘要： A continuous-time delta-sigma Analog to Digital Converter (ADC) with a compact structure comprises a loop filter, a summing circuit, a quantizer, and a current Digital to Analog Converter (DAC). The loop filter is utilized for receiving and noise-shaping an analog input signal, and accordingly outputting a positive and a negative loop voltages. The summing circuit comprises a positive and a negative summing resistors. The summing resistors are utilized for transforming a positive and negative feedback currents to be a positive and a negative feedback voltages, and summing the loop voltages and the feedback voltages so as to generate a positive and a negative summing voltages, respectively. The quantizer is utilized for outputting a digital output signal according to a difference between the positive and the negative summing voltages. The current DAC is utilized for generating the positive and the negative feedback currents according to the digital output signal.

摘要翻译： 具有紧凑结构的连续时间Δ-Σ模数转换器（ADC）包括环路滤波器，加法电路，量化器和当前的数模转换器（DAC）。 环路滤波器用于接收和噪声整形模拟输入信号，从而输出正和负的环路电压。 求和电路包括正和负相加电阻。 求和电阻用于将正和负反馈电流变换为正和负反馈电压，并将回路电压和反馈电压相加，以分别产生正负相加电压。 量化器用于根据正和负求和电压之间的差异输出数字输出信号。 电流DAC用于根据数字输出信号产生正和负反馈电流。