公开(公告)号：US20050278677A1

公开(公告)日：2005-12-15

申请号：US10864951

申请日：2004-06-10

Applicant: Chew Ang ,  Gang Chen ,  Shyue Tan

Inventor： Chew Ang ,  Gang Chen ,  Shyue Tan

IPC: G01R31/26 ,  G06F17/50 ,  H01L23/544 ,  H01L25/00 ,  H03K19/00

CPC classification number: H01L22/34 ,  G01R31/2628 ,  G01R31/2642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NBTI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode, and a PMOS FET device under test (DUT). The inverter assures the proper 180 degree phase relationship between the test device source and gate voltage while the imbedded electronic switches provide isolation of the test device during DC characterization testing. Another embodiment of the invention enables the testing of multiple devices under test (DUT's).

Abstract translation: 本发明描述了一种新颖的测试结构和工艺，以创建用于负偏压温度不稳定（NBTI）的PMOS器件的自动动态应力测试的结构。 本发明由集成逆变器，用于从应力模式切换到器件直流表征测量模式的两个集成电子开关以及被测试的PMOS FET器件（DUT）组成。 在DC特性测试期间，嵌入式电子开关提供测试设备的隔离，逆变器确保测试设备源和栅极电压之间正确的180度相位关系。 本发明的另一个实施例能够测试被测试的多个器件（DUT）。

公开(公告)号：US20060105533A1

公开(公告)日：2006-05-18

申请号：US10990180

申请日：2004-11-16

Applicant: Yung Chong ,  Liang Hsia ,  Chew Ang

Inventor： Yung Chong ,  Liang Hsia ,  Chew Ang

IPC: H01L21/8228

CPC classification number: H01L21/823807

Abstract: The embodiments provide a structure and a method of manufacturing a semiconductor structure that has a different material in the area where PMOS devices will be formed than in the area where NMOS devices will be formed which is characterized as follows. An embodiment comprises the following steps. A substrate is provided. The substrate has a NMOS area and a PMOS area. We form a NMOS mask over the NMOS area. We form a first semiconductor layer over the PMOS area. We remove the mask. We form a second semiconductor layer over the NMOS area. Then we form an isolation region in the substrate between at least portions of the NMOS and the PMOS areas. We form PMOS devices in the PMOS area and form NMOS devices in the NMOS area.

Abstract translation: 实施例提供一种制造半导体结构的结构和方法，该半导体结构在将要形成PMOS器件的区域中将具有不同于在其上将形成NMOS器件的区域中的材料，其特征如下。 实施例包括以下步骤。 提供基板。 衬底具有NMOS区域和PMOS区域。 我们在NMOS区域上形成NMOS掩模。 我们在PMOS区域上形成第一半导体层。 我们删除面具。 我们在NMOS区域上形成第二个半导体层。 然后，在NMOS和PMOS区域的至少一部分之间，在衬底中形成隔离区。 我们在PMOS区域中形成PMOS器件，并在NMOS区域中形成NMOS器件。

公开(公告)号：US20050118780A1

公开(公告)日：2005-06-02

申请号：US10972551

申请日：2004-10-25

Applicant: Subramanian Balakumar ,  Chew Ang ,  Jia Zheng ,  Paul Proctor

Inventor： Subramanian Balakumar ,  Chew Ang ,  Jia Zheng ,  Paul Proctor

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8234 ,  H01L21/8244 ,  H01L21/8242 ,  H01L21/20

CPC classification number: H01L28/56 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L28/90

Abstract: An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of layers either 4/4, 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques is used for this type layer growth process

Abstract translation: 一种制造高介电常数MIM电容器的改进和新工艺。 这些高介电常数MIM电容器满足RF和模拟电路应用两者所需的所有严格要求。 对于高介电常数MIM电容器，金属由双重镶嵌工艺中的铜电极组成。 超级晶格的介电常数与总体厚度的关系由4/4，2/2和1/1人造层的层数控制。 因此，可以容易地控制膜的厚度。 介电常数的增强是由于界面。 接近900的介电常数可以很容易地达到250埃厚的超晶格。 MBE，分子束外延或ALCVD，原子层CVD技术用于这种类型的层生长过程

公开(公告)号：US20050101083A1

公开(公告)日：2005-05-12

申请号：US10995849

申请日：2004-11-23

Applicant: Chew Ang ,  Eng-Hua Lim ,  Randall Cha ,  Jia Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

Inventor： Chew Ang ,  Eng-Hua Lim ,  Randall Cha ,  Jia Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

IPC: H01L21/268 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L29/4933 ,  H01L21/268 ,  H01L21/28061 ,  H01L21/823842

Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.