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公开(公告)号：US07129789B2
公开(公告)日：2006-10-31
申请号：US11027966
申请日：2005-01-03
申请人： Chi-Ming Hsiao , Chang-Fu Kuo
发明人： Chi-Ming Hsiao , Chang-Fu Kuo
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03D13/004 , H03L7/081 , H03L7/18
摘要： A fast-locking apparatus and method for frequency synthesis. A transition detector receives a first pulse signal indicative that the phase of an input signal leads that of a reference signal, receives a second pulse signal indicative that the phase of the input signal lags that of the reference signal, and generates a state signal indicative of whether the first pulse signal is ahead of the second pulse signal. A pulse-width detector generates a first width signal indicative of into which range the width of the first pulse signal falls; another pulse-width detector generates a second width signal indicative of into which range the width of the second pulse signal falls. According to the state signal and the first and the second width signals, control logic generates a regulation signal for use in adjusting the frequency of the input signal.
摘要翻译： 一种用于频率合成的快速锁定装置和方法。 转换检测器接收指示输入信号的相位导致参考信号的相位的第一脉冲信号，接收指示输入信号的相位滞后于参考信号的相位的第二脉冲信号，并产生指示 第一脉冲信号是否在第二脉冲信号之前。 脉冲宽度检测器产生指示第一脉冲信号的宽度落入哪个范围的第一宽度信号; 另一个脉冲宽度检测器产生指示第二脉冲信号的宽度落入哪个范围的第二宽度信号。 根据状态信号和第一和第二宽度信号，控制逻辑产生用于调节输入信号频率的调节信号。
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公开(公告)号：US06759838B2
公开(公告)日：2004-07-06
申请号：US10107359
申请日：2002-03-28
申请人： Kuang-Chung Tao , Chi-Ming Hsiao , Chang-Fu Kuo
发明人： Kuang-Chung Tao , Chi-Ming Hsiao , Chang-Fu Kuo
IPC分类号： G01R2312
CPC分类号： H03L7/107 , H03L7/087 , H03L7/0891 , H03L7/095 , H03L7/1077
摘要： A phase-locked loop with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. In addition, the dual-mode phase/frequency detector includes a digital phase/frequency detector, an analog phase/frequency detector, a charge pump, and a control unit. When the phase-locked loop circuit starts, the control unit causes a detection output signal from the dual-mode phase/frequency detector to correspond to a digital signal from the digital phase/frequency detector. When the phase-locked loop circuit approaches a lock state, the control unit causes the detection output signal to correspond to an analog signal from the analog phase/frequency detector. The phase-locked loop with dual-mode phase/frequency detection has the advantages of providing linear characteristics, fast switching speed, and high sensitivity.
摘要翻译： 提供了具有双模相位/频率检测的锁相环。 锁相环电路包括双模相位/频率检测器，环路滤波器，压控振荡器和变频器。 此外，双模相位/频率检测器包括数字相位/频率检测器，模拟相位/频率检测器，电荷泵和控制单元。 当锁相环电路启动时，控制单元使得来自双模相位/频率检测器的检测输出信号对应于来自数字相位/频率检测器的数字信号。 当锁相环电路接近锁定状态时，控制单元使得检测输出信号对应于来自模拟相位/频率检测器的模拟信号。 具有双模相位/频率检测的锁相环具有线性特性，切换速度快，灵敏度高的优点。
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公开(公告)号：US08239202B2
公开(公告)日：2012-08-07
申请号：US12343370
申请日：2008-12-23
申请人： Chi-Ming Hsiao
发明人： Chi-Ming Hsiao
CPC分类号： H04W4/18
摘要： A method and system for audibly outputting text messages includes: setting a vocalizing function for audibly outputting text messages, searching a character speech library for each character of a received text message, and acquiring pronunciation data of each character of the received text message. The method and the system further includes vocalizing the pronunciation data of each character of the received text message, generating a voice message, and audibly outputting the generated voice message.
摘要翻译： 用于可听输出文本消息的方法和系统包括：设置用于可听地输出文本消息的发音功能，为接收的文本消息的每个字符搜索字符语音库，以及获取所接收的文本消息的每个字符的发音数据。 所述方法和系统还包括发出接收到的文本消息的每个字符的发音数据，生成语音消息，并且可听地输出生成的语音消息。
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4.发明授权Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit 有权开关电容器电路能够最小化压控振荡器电路中的时钟馈通效应公开(公告)号：US06815996B1
公开(公告)日：2004-11-09
申请号：US10605095
申请日：2003-09-09
申请人： Chi-Ming Hsiao
发明人： Chi-Ming Hsiao
IPC分类号： G06F764
CPC分类号： H03B5/1206 , H03B5/124 , H03B5/1265 , H03B2200/005 , H03J2200/10
摘要： A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in an order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect. The subthreshold and leakage currents passing through the largest switch elements are blocked by the use of an additional switch element to isolate the largest switch element.
摘要翻译： 一种用于压控振荡器（VCO）的开关电容器电路，其能够在开关电容器电路被切断时最小化时钟馈通效应和VCO输出频率中的不期望的瞬时频率漂移。 通过将开关电容器电路从接通状态逐渐切换到断开状态，可以使时钟馈通效应最小化。 当将开关电容器电路切换到关闭状态时，控制信号被排序，以基于减小的开关尺寸的顺序关闭开关元件。 最小的开关元件可以将低通滤波器添加到其控制端子，以进一步减小时钟馈通效应。 通过最大开关元件的亚阈值和漏电流通过使用额外的开关元件来隔离最大的开关元件而被阻断。
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公开(公告)号：US07019499B2
公开(公告)日：2006-03-28
申请号：US10709636
申请日：2004-05-19
申请人： Chi-Kun Chiu , Chi-Ming Hsiao
发明人： Chi-Kun Chiu , Chi-Ming Hsiao
IPC分类号： G05F1/40
CPC分类号： G05F1/56
摘要： A low noise voltage regulator circuit with fast stable output voltage is disclosed. The low noise voltage regulator circuit contains a reference voltage generator, for generating a reference voltage; a switching circuit, which is electrically coupled to the output of reference voltage generator and has two states; and a stabilizing circuit. When the switching circuit is at a first state, the reference voltage is coupled to the stabilizing circuit without being filtered; when the switching circuit is at a second state, the reference voltage is filtered by a low pass filter before being coupled to the stabilizing circuit. A switching control signal is used to switch the switching circuit between the two states. The filtered reference voltage is used to generate a low noise regulated output voltage.
摘要翻译： 公开了一种具有快速稳定输出电压的低噪声稳压电路。 低噪声稳压器电路包含用于产生参考电压的参考电压发生器; 开关电路，其电耦合到参考电压发生器的输出并具有两种状态; 和稳定电路。 当开关电路处于第一状态时，参考电压被耦合到稳定电路而不被滤波; 当开关电路处于第二状态时，在耦合到稳定电路之前，参考电压被低通滤波器滤波。 开关控制信号用于在两种状态之间切换开关电路。 滤波后的参考电压用于产生低噪声调节输出电压。
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公开(公告)号：US20090313022A1
公开(公告)日：2009-12-17
申请号：US12343370
申请日：2008-12-23
申请人： CHI-MING HSIAO
发明人： CHI-MING HSIAO
CPC分类号： H04W4/18
摘要： A method and system for audibly outputting text messages includes: setting a vocalizing function for audibly outputting text messages, searching a character speech library for each character of a received text message, and acquiring pronunciation data of each character of the received text message. The method and the system further includes vocalizing the pronunciation data of each character of the received text message, generating a voice message, and audibly outputting the generated voice message.
摘要翻译： 用于可听输出文本消息的方法和系统包括：设置用于可听地输出文本消息的发音功能，为接收的文本消息的每个字符搜索字符语音库，以及获取所接收的文本消息的每个字符的发音数据。 所述方法和系统还包括发出接收到的文本消息的每个字符的发音数据，生成语音消息，并且可听地输出生成的语音消息。
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公开(公告)号：US07446519B2
公开(公告)日：2008-11-04
申请号：US11494634
申请日：2006-07-28
CPC分类号： H02M3/1588 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
摘要： A switching regulator automatically operates in pulse width modulation (“PWM”) mode for high load currents and in burst mode for low load currents. The switching regulator includes a pair of switches to provide a regulated current to a load. The switching regulator further includes a multi-input comparator. A first input of the comparator is coupled to an output of the pair of switches. A second input of the comparator is coupled to a filtered version of the output and a third input is coupled to a reference waveform. The first, second and third inputs of the comparator form a combined input signal to the comparator. An output signal of the comparator is generated by comparing the combined input signal to a threshold of the comparator. The output signal determines a switching frequency of the pair of switches such that the switching frequency is automatically reduced when the load is decreased.
摘要翻译： 开关稳压器在高负载电流下以脉冲宽度调制（“PWM”）模式自动工作，并且在低负载电流下以脉冲串模式工作。 开关调节器包括一对向负载提供调节电流的开关。 开关调节器还包括多输入比较器。 比较器的第一输入耦合到该对开关的输出端。 比较器的第二输入耦合到输出的滤波版本，第三输入耦合到参考波形。 比较器的第一，第二和第三输入端形成到比较器的组合输入信号。 通过将组合的输入信号与比较器的阈值进行比较来产生比较器的输出信号。 输出信号决定了一对开关的开关频率，使负载减小时开关频率自动降低。
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公开(公告)号：US20070040537A1
公开(公告)日：2007-02-22
申请号：US11494634
申请日：2006-07-28
申请人： Khim Low , David Ho , Chi-Ming Hsiao , Hua Chan
发明人： Khim Low , David Ho , Chi-Ming Hsiao , Hua Chan
IPC分类号： G05F1/00
CPC分类号： H02M3/1588 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
摘要： A switching regulator automatically operates in pulse width modulation (“PWM”) mode for high load currents and in burst mode for low load currents. The switching regulator includes a pair of switches to provide a regulated current to a load. The switching regulator further includes a multi-input comparator. A first input of the comparator is coupled to an output of the pair of switches. A second input of the comparator is coupled to a filtered version of the output and a third input is coupled to a reference waveform. The first, second and third inputs of the comparator form a combined input signal to the comparator. An output signal of the comparator is generated by comparing the combined input signal to a threshold of the comparator. The output signal determines a switching frequency of the pair of switches such that the switching frequency is automatically reduced when the load is decreased.
摘要翻译： 开关稳压器在高负载电流下以脉冲宽度调制（“PWM”）模式自动工作，并且在低负载电流下以脉冲串模式工作。 开关调节器包括一对向负载提供调节电流的开关。 开关调节器还包括多输入比较器。 比较器的第一输入耦合到该对开关的输出端。 比较器的第二输入耦合到输出的滤波版本，第三输入耦合到参考波形。 比较器的第一，第二和第三输入端形成到比较器的组合输入信号。 通过将组合的输入信号与比较器的阈值进行比较来产生比较器的输出信号。 输出信号决定了一对开关的开关频率，使负载减小时开关频率自动降低。
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公开(公告)号：US20060145732A1
公开(公告)日：2006-07-06
申请号：US11027966
申请日：2005-01-03
申请人： Chi-Ming Hsiao , Chang-Fu Kuo
发明人： Chi-Ming Hsiao , Chang-Fu Kuo
IPC分类号： H03B21/00
CPC分类号： H03L7/10 , H03D13/004 , H03L7/081 , H03L7/18
摘要： A fast-locking apparatus and method for frequency synthesis. A transition detector receives a first pulse signal indicative that the phase of an input signal leads that of a reference signal, receives a second pulse signal indicative that the phase of the input signal lags that of the reference signal, and generates a state signal indicative of whether the first pulse signal is ahead of the second pulse signal. A pulse-width detector generates a first width signal indicative of into which range the width of the first pulse signal falls; another pulse-width detector generates a second width signal indicative of into which range the width of the second pulse signal falls. According to the state signal and the first and the second width signals, control logic generates a regulation signal for use in adjusting the frequency of the input signal.
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