公开(公告)号：US07995979B2

公开(公告)日：2011-08-09

申请号：US12041664

申请日：2008-03-04

申请人： Chao-Hsin Lu ,  Chang-Fu Kuo

发明人： Chao-Hsin Lu ,  Chang-Fu Kuo

IPC分类号： H04B17/02 ,  H04B7/00

CPC分类号： G01S19/23 ,  H03G3/3052

摘要： A wireless receiver with automatic gain control and a method for automatic gain control of a receiving circuit utilized in a wireless receiver are provided. The receiving circuit includes a programmable gain amplifier and a low noise amplifier, and the method includes: comparing a gain code of the programmable gain amplifier with a predetermined code range, wherein the gain code is determined by a frequency signal received through the low noise amplifier; and adjusting a gain of the low noise amplifier when the gain code is out of the predetermined code range.

摘要翻译： 提供一种具有自动增益控制的无线接收机和用于无线接收机中的接收电路的自动增益控制方法。 接收电路包括可编程增益放大器和低噪声放大器，该方法包括：将可编程增益放大器的增益代码与预定代码范围进行比较，其中增益代码由通过低噪声放大器接收的频率信号确定 ; 以及当所述增益代码超出所述预定代码范围时调整所述低噪声放大器的增益。

公开(公告)号：US20110116578A1

公开(公告)日：2011-05-19

申请号：US13013552

申请日：2011-01-25

申请人： Chang-Fu Kuo ,  Min Jie Wu ,  Beng Hwee Ong ,  Wee Liang Lien

发明人： Chang-Fu Kuo ,  Min Jie Wu ,  Beng Hwee Ong ,  Wee Liang Lien

IPC分类号： H03D3/24 ,  H04B1/10

CPC分类号： H04B1/28 ,  H04B1/3805

摘要： A receiver includes a mixer, a poly phase filter, a channel select filter, an analog-to-digital converter and a HI/LO side reject selection unit. The mixer downconverts a signal to generate an in-phase signal and a quadrature signal. The poly phase filter for generates differential IF signals based on the in-phase signal and the quadrature signal. The channel select filter filters out unwanted channel signals from the differential IF signals. The analog-to-digital converter converts the filtered signal into a digital output signal. The HI/LO side reject selection unit is coupled between the mixer and the poly phase filter and capable of rejecting image signals while the mixer is at a high side frequency or at a low side frequency.

摘要翻译： 接收机包括混频器，多相滤波器，通道选择滤波器，模数转换器和HI / LO侧拒绝选择单元。 混频器将信号下变频以产生同相信号和正交信号。 多相滤波器，用于基于同相信号和正交信号产生差分IF信号。 通道选择滤波器滤除差分IF信号中不需要的通道信号。 模数转换器将滤波后的信号转换为数字输出信号。 HI / LO侧拒绝选择单元耦合在混频器和多相滤波器之间，并且能够在混频器处于高侧频率或低频率时拒绝图像信号。

公开(公告)号：US07508277B2

公开(公告)日：2009-03-24

申请号：US11079220

申请日：2005-03-15

申请人： Chang-Fu Kuo ,  Po-Sen Tseng ,  Shou-Tsung Wang ,  Ling-Wei Ko

发明人： Chang-Fu Kuo ,  Po-Sen Tseng ,  Shou-Tsung Wang ,  Ling-Wei Ko

IPC分类号： H03L7/085

CPC分类号： H03L7/085 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/1072 ,  H03L7/18 ,  H03L7/185 ,  H03L2207/05

摘要： The invention provides a phase-locked loop (PLL). Since a loop bandwidth of the PLL is a function of a gain of a phase detector and a gain of a voltage controlled oscillator (VCO), by adjusting the gain of the phase detector, the variation of the gain of the VCO (i.e., the tuning sensitivity) is compensated, so that the loop bandwidth of the PLL becomes more stable.

摘要翻译： 本发明提供一种锁相环（PLL）。 由于PLL的环路带宽是相位检测器的增益和压控振荡器（VCO）的增益的函数，所以通过调整相位检测器的增益，VCO的增益的变化（即， 调谐灵敏度）被补偿，使得PLL的环路带宽变得更加稳定。

公开(公告)号：US20070132491A1

公开(公告)日：2007-06-14

申请号：US11164956

申请日：2005-12-12

申请人： Chang-Fu Kuo ,  Tser-Yu Lin

发明人： Chang-Fu Kuo ,  Tser-Yu Lin

IPC分类号： H03L7/06

CPC分类号： H03L7/0898

摘要： The present invention provides a charge pump in a phase lock loop circuit. The phase lock loop circuit comprises a voltage controlled oscillator (VCO) for producing a variable frequency output signal in response to a VCO control voltage. The charge pump comprises a current generating module for providing a first current, a second circuit for providing a bias current according to a bias control signal, a current mirror circuit that comprises a first current generating unit for generating a third current proportional to a sum of the first current and the second current, and a second current generating unit for generating a fourth current proportional to the sum of the first current and the second current, a first switch for sourcing the third current according to a first control signal and a second switch for sinking the fourth current according to a second control signal.

摘要翻译： 本发明提供一种锁相环电路中的电荷泵。 锁相环电路包括用于响应于VCO控制电压产生可变频率输出信号的压控振荡器（VCO）。 电荷泵包括用于提供第一电流的电流产生模块，用于根据偏置控制信号提供偏置电流的第二电路;电流镜电路，包括第一电流产生单元，用于产生与第一电流成正比的第三电流 第一电流和第二电流;以及第二电流产生单元，用于产生与第一电流和第二电流的和成比例的第四电流;第一开关，用于根据第一控制信号提供第三电流;以及第二开关 用于根据第二控制信号吸收第四电流。

公开(公告)号：US07129789B2

公开(公告)日：2006-10-31

申请号：US11027966

申请日：2005-01-03

申请人： Chi-Ming Hsiao ,  Chang-Fu Kuo

发明人： Chi-Ming Hsiao ,  Chang-Fu Kuo

IPC分类号： H03L7/00

CPC分类号： H03L7/10 ,  H03D13/004 ,  H03L7/081 ,  H03L7/18

摘要： A fast-locking apparatus and method for frequency synthesis. A transition detector receives a first pulse signal indicative that the phase of an input signal leads that of a reference signal, receives a second pulse signal indicative that the phase of the input signal lags that of the reference signal, and generates a state signal indicative of whether the first pulse signal is ahead of the second pulse signal. A pulse-width detector generates a first width signal indicative of into which range the width of the first pulse signal falls; another pulse-width detector generates a second width signal indicative of into which range the width of the second pulse signal falls. According to the state signal and the first and the second width signals, control logic generates a regulation signal for use in adjusting the frequency of the input signal.

摘要翻译： 一种用于频率合成的快速锁定装置和方法。 转换检测器接收指示输入信号的相位导致参考信号的相位的第一脉冲信号，接收指示输入信号的相位滞后于参考信号的相位的第二脉冲信号，并产生指示 第一脉冲信号是否在第二脉冲信号之前。 脉冲宽度检测器产生指示第一脉冲信号的宽度落入哪个范围的第一宽度信号; 另一个脉冲宽度检测器产生指示第二脉冲信号的宽度落入哪个范围的第二宽度信号。 根据状态信号和第一和第二宽度信号，控制逻辑产生用于调节输入信号频率的调节信号。

公开(公告)号：US06759838B2

公开(公告)日：2004-07-06

申请号：US10107359

申请日：2002-03-28

申请人： Kuang-Chung Tao ,  Chi-Ming Hsiao ,  Chang-Fu Kuo

发明人： Kuang-Chung Tao ,  Chi-Ming Hsiao ,  Chang-Fu Kuo

IPC分类号： G01R2312

CPC分类号： H03L7/107 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/1077

摘要： A phase-locked loop with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. In addition, the dual-mode phase/frequency detector includes a digital phase/frequency detector, an analog phase/frequency detector, a charge pump, and a control unit. When the phase-locked loop circuit starts, the control unit causes a detection output signal from the dual-mode phase/frequency detector to correspond to a digital signal from the digital phase/frequency detector. When the phase-locked loop circuit approaches a lock state, the control unit causes the detection output signal to correspond to an analog signal from the analog phase/frequency detector. The phase-locked loop with dual-mode phase/frequency detection has the advantages of providing linear characteristics, fast switching speed, and high sensitivity.

摘要翻译： 提供了具有双模相位/频率检测的锁相环。 锁相环电路包括双模相位/频率检测器，环路滤波器，压控振荡器和变频器。 此外，双模相位/频率检测器包括数字相位/频率检测器，模拟相位/频率检测器，电荷泵和控制单元。 当锁相环电路启动时，控制单元使得来自双模相位/频率检测器的检测输出信号对应于来自数字相位/频率检测器的数字信号。 当锁相环电路接近锁定状态时，控制单元使得检测输出信号对应于来自模拟相位/频率检测器的模拟信号。 具有双模相位/频率检测的锁相环具有线性特性，切换速度快，灵敏度高的优点。

公开(公告)号：US20060145732A1

公开(公告)日：2006-07-06

申请号：US11027966

申请日：2005-01-03

申请人： Chi-Ming Hsiao ,  Chang-Fu Kuo

发明人： Chi-Ming Hsiao ,  Chang-Fu Kuo

IPC分类号： H03B21/00

CPC分类号： H03L7/10 ,  H03D13/004 ,  H03L7/081 ,  H03L7/18

摘要： A fast-locking apparatus and method for frequency synthesis. A transition detector receives a first pulse signal indicative that the phase of an input signal leads that of a reference signal, receives a second pulse signal indicative that the phase of the input signal lags that of the reference signal, and generates a state signal indicative of whether the first pulse signal is ahead of the second pulse signal. A pulse-width detector generates a first width signal indicative of into which range the width of the first pulse signal falls; another pulse-width detector generates a second width signal indicative of into which range the width of the second pulse signal falls. According to the state signal and the first and the second width signals, control logic generates a regulation signal for use in adjusting the frequency of the input signal.

公开(公告)号：US07961057B2

公开(公告)日：2011-06-14

申请号：US12200009

申请日：2008-08-28

申请人： Beng Hwee Ong ,  Minjie Wu ,  Wee Liang Lien ,  Chang-Fu Kuo

发明人： Beng Hwee Ong ,  Minjie Wu ,  Wee Liang Lien ,  Chang-Fu Kuo

IPC分类号： H03B19/12

CPC分类号： H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

摘要： An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency.

摘要翻译： 提供集成电路和装置。 集成电路包括偏置电路，LC谐振电路和电流模式逻辑（CML）分频器。 偏置电路产生第一和第二偏置电压。 LC谐振器电路产生具有振荡频率的振荡信号。 耦合到偏置电路和LC谐振器电路的由第一和第二偏置电压偏置的CML分频器接收振荡信号以产生具有振荡频率的分数速率的输出频率的输出信号。 振荡信号包括AC和DC分量，CML分频器接收AC分量以确定注入频率，并重新使用DC分量来提供尾电流以确定CML分频器的固有频率。 输出频率由注入频率和固有频率决定。

公开(公告)号：US20100052803A1

公开(公告)日：2010-03-04

申请号：US12200009

申请日：2008-08-28

申请人： Beng Hwee ONG ,  Minjie WU ,  Wee Liang LIEN ,  Chang-Fu KUO

发明人： Beng Hwee ONG ,  Minjie WU ,  Wee Liang LIEN ,  Chang-Fu KUO

IPC分类号： H03L7/099

CPC分类号： H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

摘要： An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency.

摘要翻译： 提供集成电路和装置。 集成电路包括偏置电路，LC谐振电路和电流模式逻辑（CML）分频器。 偏置电路产生第一和第二偏置电压。 LC谐振器电路产生具有振荡频率的振荡信号。 耦合到由第一和第二偏置电压偏置的偏置电路和LC谐振器电路的CML分频器接收振荡信号以产生具有振荡频率的分数速率的输出频率的输出信号。 振荡信号包括AC和DC分量，CML分频器接收AC分量以确定注入频率，并重新使用DC分量来提供尾电流以确定CML分频器的固有频率。 输出频率由注入频率和固有频率决定。

公开(公告)号：US07899137B2

公开(公告)日：2011-03-01

申请号：US11617962

申请日：2006-12-29

申请人： Chang-Fu Kuo ,  Min Jie Wu ,  Beng Hwee Ong ,  Wee Liang Lien

发明人： Chang-Fu Kuo ,  Min Jie Wu ,  Beng Hwee Ong ,  Wee Liang Lien

IPC分类号： H03D3/24 ,  H04L27/22

CPC分类号： H04B1/28 ,  H04B1/3805

摘要： A Global Positioning System (GPS) receiver integrated with a cellular phone system, comprising a single-balanced mixer, a poly phase filter, a channel select filter, an analog-to-digital converter, a reference frequency source, and a PLL unit is disclosed. The single-balanced mixer downconverts a GPS signal to generate an in-phase signal I and a quadrature signal Q. The poly phase filter generates an IF signal based on the in-phase signal I and the quadrature signal Q. The channel select filter receives the IF signal to filter unwanted channel signals. The analog-to-digital converter converts the signal from the channel select filter to a digital output signal. The reference frequency source provides a reference frequency to the analog-to-digital converter. The PLL unit receives the reference frequency for generating a clock signal to the single-balanced mixer for downconversion.

摘要翻译： 与蜂窝电话系统集成的全球定位系统（GPS）接收机，包括单平衡混频器，多相滤波器，信道选择滤波器，模数转换器，参考频率源和PLL单元。 披露 单平衡混频器将GPS信号下变频以产生同相信号I和正交信号Q.多相滤波器基于同相信号I和正交信号Q产生IF信号。频道选择滤波器接收 IF信号滤除不需要的信道信号。 模数转换器将来自通道选择滤波器的信号转换为数字输出信号。 参考频率源为模数转换器提供参考频率。 PLL单元接收用于产生用于下变频的单平衡混频器的时钟信号的参考频率。