公开(公告)号：US20070051956A1

公开(公告)日：2007-03-08

申请号：US11162159

申请日：2005-08-31

申请人： Chih-Jen Shih ,  Chun-Hsiang Fang ,  Te-Hua Teng ,  Chia-Chien Lu

发明人： Chih-Jen Shih ,  Chun-Hsiang Fang ,  Te-Hua Teng ,  Chia-Chien Lu

IPC分类号： H01L29/00

CPC分类号： H01L29/78645 ,  H01L29/78624

摘要： A thin film transistor having a substrate, a gate insulating layer, a double-gate structure, a first lightly doped region, and a second lightly doped region. The substrate has a source region and a drain region disposed on its opposite sides, a heavily doped region between source region and drain region, a first channel region between heavily doped region and source region and a second channel region between heavily doped region and drain region. The gate insulating layer covers the substrate. The double-gate structure has a first gate and a second gate disposed on gate insulating layer above the first and the second channel region, respectively. The first lightly doped region is disposed between second channel region and heavily doped region and the second lightly doped region between second channel region and drain region. The length of second lightly doped region is greater than that of first lightly doped region.

摘要翻译： 一种具有衬底，栅极绝缘层，双栅极结构，第一轻掺杂区和第二轻掺杂区的薄膜晶体管。 衬底具有设置在其相对侧上的源极区域和漏极区域，源极区域和漏极区域之间的重掺杂区域，重掺杂区域和源极区域之间的第一沟道区域以及重掺杂区域和漏极区域之间的第二沟道区域 。 栅极绝缘层覆盖基板。 双栅结构具有分别设置在第一和第二沟道区上方的栅极绝缘层上的第一栅极和第二栅极。 第一轻掺杂区域设置在第二沟道区域和重掺杂区域之间，第二轻掺杂区域设置在第二沟道区域和漏极区域之间。 第二轻掺杂区域的长度大于第一轻掺杂区域的长度。

公开(公告)号：US20070155135A1

公开(公告)日：2007-07-05

申请号：US11306899

申请日：2006-01-16

申请人： Yun-Pei Yang ,  Te-Hua Teng ,  Chih-Jen Shih ,  Chia-Chien Lu

发明人： Yun-Pei Yang ,  Te-Hua Teng ,  Chih-Jen Shih ,  Chia-Chien Lu

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02686 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/1277

摘要： A method of fabricating a polysilicon layer is provided. A substrate having a front surface and a back surface is provided. A buffer layer, an amorphous layer and a cap layer are sequentially formed on the front surface of the substrate. The cap layer is patterned to form a patterned cap layer exposing a portion of the amorphous layer, wherein the exposed portion of the amorphous layer is a crystallization initial region. A metallic catalytic layer is formed on the patterned cap layer, wherein the metallic catalytic layer contacts with the crystallization initial region of the amorphous layer. A laser annealing process is performed through the back surface of the substrate so that the amorphous layer is crystallized and transformed into a polysilicon layer from the crystallization initial region.

摘要翻译： 提供一种制造多晶硅层的方法。 提供具有前表面和后表面的基板。 缓冲层，非晶层和盖层依次形成在基板的前表面上。 图案化盖层以形成暴露非晶层的一部分的图案化盖层，其中非晶层的暴露部分是结晶初始区域。 在图案化盖层上形成金属催化剂层，其中金属催化剂层与非晶层的结晶初始区域接触。 通过衬底的背面进行激光退火处理，使得非晶层从结晶初始区域结晶化并转变为多晶硅层。

公开(公告)号：US20070054442A1

公开(公告)日：2007-03-08

申请号：US11223659

申请日：2005-09-08

申请人： Po-Chih Liu ,  Chun-Hsiang Fang ,  Ming-Che Ho ,  Chia-Chien Lu

发明人： Po-Chih Liu ,  Chun-Hsiang Fang ,  Ming-Che Ho ,  Chia-Chien Lu

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/458 ,  H01L29/665 ,  H01L29/66757 ,  H01L29/78675

摘要： A method for manufacturing a thin film transistor is provided. First, a poly-silicon island is formed on a substrate. Then, a patterned gate dielectric layer and a gate are formed on the poly-silicon island. Next, a source/drain is formed in the poly-silicon island beside the gate, wherein the region between the source/drain is a channel. Furthermore, a metal layer is formed on the substrate to cover the gate, the patterned gate dielectric layer and the poly-silicon island. Moreover, the metal layer above the source/drain will react with the poly-silicon island to form a silicide layer. Then, the non-reacted metal layer is removed. Afterwards, an inter-layer dielectric (ILD) is formed to cover the substrate. Then, the inter-layer dielectric above the source/drain is removed to form a source/drain contacting hole, wherein the silicide layer is used as an etching stopper.

摘要翻译： 提供了制造薄膜晶体管的方法。 首先，在基板上形成多晶硅岛。 然后，在多晶硅岛上形成图案化的栅介质层和栅极。 接下来，在栅极旁边的多晶硅岛中形成源极/漏极，其中源极/漏极之间的区域是沟道。 此外，在基板上形成金属层以覆盖栅极，图案化栅介质层和多晶硅岛。 此外，源极/漏极之上的金属层将与多晶硅岛反应形成硅化物层。 然后，除去未反应的金属层。 之后，形成层间电介质（ILD）以覆盖基板。 然后，除去源极/漏极之上的层间电介质以形成源极/漏极接触孔，其中硅化物层用作蚀刻停止层。

公开(公告)号：US20070051993A1

公开(公告)日：2007-03-08

申请号：US11222923

申请日：2005-09-08

申请人： Ming-Che Ho ,  Yun-Pei Yang ,  Po-Chih Liu ,  Chia-Chien Lu

发明人： Ming-Che Ho ,  Yun-Pei Yang ,  Po-Chih Liu ,  Chia-Chien Lu

IPC分类号： H01L29/94 ,  G12B21/02

CPC分类号： H01L29/78609 ,  H01L29/4908 ,  H01L29/66757

摘要： A method of forming a thin film transistor is provided. First, an amorphous silicon layer is formed on a substrate. Next, a first gate insulating layer is formed on the amorphous silicon layer. Then, an annealing process is performed so that the amorphous silicon layer is melted and re-crystallized to form a poly silicon layer. Next, the first insulating layer and the poly silicon layer are patterned to form an island. Then, a gate electrode is formed on the island. Finally, a source region and a drain region are formed inside the poly silicon layer of the island. After the annealing process is performed, the boundary between the poly silicon layer and the gate insulating layer becomes denser, so that the current leakage of the thin film transistor can be reduced.

摘要翻译： 提供一种形成薄膜晶体管的方法。 首先，在基板上形成非晶硅层。 接下来，在非晶硅层上形成第一栅极绝缘层。 然后，进行退火处理，使得非晶硅层熔融并再结晶以形成多晶硅层。 接下来，对第一绝缘层和多晶硅层进行图案化以形成岛。 然后，在岛上形成栅电极。 最后，在岛的多晶硅层的内部形成源极区域和漏极区域。 在进行退火处理之后，多晶硅层和栅极绝缘层之间的边界变得更致密，从而可以减小薄膜晶体管的漏电流。

公开(公告)号：US20070093003A1

公开(公告)日：2007-04-26

申请号：US11163602

申请日：2005-10-25

申请人： Chuan-Yi Wu ,  Yung-Chia Kuan ,  Chia-Chien Lu ,  Chin-Chuan Lai

发明人： Chuan-Yi Wu ,  Yung-Chia Kuan ,  Chia-Chien Lu ,  Chin-Chuan Lai

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/41733 ,  H01L29/458 ,  H01L29/66742 ,  Y10S438/906

摘要： A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor layer in sequence. The second conductive layer is patterned such that each side of thereof above the gate has a taper profile and the first conductive layer is exposed. A first plasma process is performed to transform the surface and the taper profile of the second conductive layer into a first protection layer. The first conductive layer not covered by the first protection layer and the second conductive layer is removed to form a source/drain. The source/drain is with fine dimensions and the diffusion of metallic ions from the second conductive layer to the patterned semiconductor layer can be avoided.

摘要翻译： 提供一种制造薄膜晶体管的方法。 首先，在基板上形成栅极。 形成栅极绝缘层以覆盖栅极。 在栅极绝缘层上形成图案化的半导体层。 依次在图案化的半导体层上形成第一和第二导电层。 第二导电层被图案化，使得栅极上方的每一侧具有锥形轮廓，并且第一导电层被暴露。 执行第一等离子体处理以将第二导电层的表面和锥形轮廓变换为第一保护层。 不被第一保护层和第二导电层覆盖的第一导电层被去除以形成源极/漏极。 源极/漏极具有精细的尺寸，并且可以避免金属离子从第二导电层到图案化半导体层的扩散。

公开(公告)号：US07229863B2

公开(公告)日：2007-06-12

申请号：US11163602

申请日：2005-10-25

申请人： Chuan-Yi Wu ,  Yung-Chia Kuan ,  Chia-Chien Lu ,  Chin-Chuan Lai

发明人： Chuan-Yi Wu ,  Yung-Chia Kuan ,  Chia-Chien Lu ,  Chin-Chuan Lai

IPC分类号： H01L21/84

CPC分类号： H01L29/41733 ,  H01L29/458 ,  H01L29/66742 ,  Y10S438/906

摘要： A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor layer in sequence. The second conductive layer is patterned such that each side of thereof above the gate has a taper profile and the first conductive layer is exposed. A first plasma process is performed to transform the surface and the taper profile of the second conductive layer into a first protection layer. The first conductive layer not covered by the first protection layer and the second conductive layer is removed to form a source/drain. The source/drain is with fine dimensions and the diffusion of metallic ions from the second conductive layer to the patterned semiconductor layer can be avoided.

摘要翻译： 提供一种制造薄膜晶体管的方法。 首先，在基板上形成栅极。 形成栅极绝缘层以覆盖栅极。 在栅极绝缘层上形成图案化的半导体层。 依次在图案化的半导体层上形成第一和第二导电层。 第二导电层被图案化，使得栅极上方的每一侧具有锥形轮廓，并且第一导电层被暴露。 执行第一等离子体处理以将第二导电层的表面和锥形轮廓变换为第一保护层。 不被第一保护层和第二导电层覆盖的第一导电层被去除以形成源极/漏极。 源极/漏极具有精细的尺寸，并且可以避免金属离子从第二导电层到图案化半导体层的扩散。