公开(公告)号：US09075613B2

公开(公告)日：2015-07-07

申请号：US13278329

申请日：2011-10-21

申请人： Hsin-Chung Chen ,  Chia-Jen Chang

发明人： Hsin-Chung Chen ,  Chia-Jen Chang

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/26 ,  G06F1/324 ,  Y02D10/172

摘要： An exemplary low power consumption circuit includes a microprocessor, a power supply switch module and a main circuit module. The microprocessor is capable of outputting a power control signal and changing a pulse characteristic of the power control signal when the microprocessor switches from a first working mode to a second working mode. The power supply switch module is capable of outputting a power supply signal. The power supply switch module is electrically coupled to the microprocessor to receive the power control signal and thereby modulates a duty cycle of the power supply signal according to a change of the pulse characteristic of the power control signal. The main circuit module is electrically coupled to the power supply switch module to receive the power supply signal and operative with energy provided by the power supply signal. Moreover, a method for reducing power consumption is also provided.

摘要翻译： 示例性的低功耗电路包括微处理器，电源开关模块和主电路模块。 当微处理器从第一工作模式切换到第二工作模式时，微处理器能够输出功率控制信号和改变功率控制信号的脉冲特性。 电源开关模块能够输出电源信号。 电源开关模块电耦合到微处理器以接收功率控制信号，从而根据功率控制信号的脉冲特性的变化来调制电源信号的占空比。 主电路模块电耦合到电源开关模块以接收电源信号并且与由电源信号提供的能量一起工作。 此外，还提供了降低功耗的方法。

公开(公告)号：US20130179758A1

公开(公告)日：2013-07-11

申请号：US13348447

申请日：2012-01-11

申请人： Guorjuh Thomas Hwang ,  Chia Jen Chang

发明人： Guorjuh Thomas Hwang ,  Chia Jen Chang

IPC分类号： H03M13/09 ,  G06F11/10

CPC分类号： H03M13/2792 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/098 ,  H03M13/6561

摘要： Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.

摘要翻译： 公开了用于交错奇偶校验计算的电路，集成电路和方法。 在一个这样的示例电路中，交错奇偶校验计算电路包括接收第一组位的第一奇偶校验电路和接收第二组位的第二奇偶校验电路。 第一组位包括第一奇偶校验位，并且在第一时钟周期期间在第一奇偶校验电路中接收。 第一奇偶校验电路产生指示第一组位的奇偶性的第一信号。 第二组位包括第二奇偶校验位，并且在第二时钟周期期间在第二奇偶校验电路中接收。 第二奇偶校验电路产生指示第二组位的奇偶性的第二信号。 组合电路将第一信号和第二信号组合成报警信号。

公开(公告)号：US07911262B2

公开(公告)日：2011-03-22

申请号：US12413596

申请日：2009-03-29

申请人： Phat Truong ,  Pauline Mai ,  Chia-Jen Chang

发明人： Phat Truong ,  Pauline Mai ,  Chia-Jen Chang

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H03K19/00384

摘要： An integrated circuit includes: a pre-driver stage, coupled to an external supply voltage, for controlling the final driver stage; a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; a compensation circuit, coupled to the pre-driver stage, for providing a bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage; and a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing a bias voltage as an input to the compensation circuit.

摘要翻译： 集成电路包括：预驱动器级，耦合到外部电源电压，用于控制最终的驱动级; 耦合到预驱动器级和外部电源电压的最终驱动器级，用于提供输出电压; 耦合到预驱动器级的补偿电路，用于向前驱动器级提供偏置电压，其补偿外部电源电压的变化，以控制通过前驱动器级的电流; 以及耦合到外部电源电压和补偿电路的偏置电路，用于提供偏置电压作为对补偿电路的输入。

公开(公告)号：US20070040076A1

公开(公告)日：2007-02-22

申请号：US11198271

申请日：2005-08-08

申请人： Chia-Jen Chang ,  Hao-Che Chang

发明人： Chia-Jen Chang ,  Hao-Che Chang

IPC分类号： F16M11/00

CPC分类号： F16M11/40 ,  B60R11/0235 ,  B60R2011/0084 ,  B60R2011/0089 ,  F16M11/12 ,  F16M11/18 ,  F16M13/02 ,  F16M13/027

摘要： A 3D supporting stand for monitors uses a plastic metal tube to serve as a movable device, such that he plastic metal tube can perform rotation and movement in multiple angles, and is extended into the holding tube for connection. By means of a latching device inside the holding tube, the plastic metal tube can be adjusted with retraction, thereby increasing an agility of the monitor supporting stand, and enabling the entire structure to move to any angle and reach to a desired position, so as to achieve a variation of 3D multiple angles, and to facilitate increasing a comfort upon viewing in compliance with ergonomics. Moreover, when the plastic metal tube is completely retracted into the holding tube, the monitor can be adjusted to be horizontally or vertically embedded into an object attached by the holding tube for collection, thereby saving a space.

摘要翻译： 用于监视器的3D支撑架使用塑料金属管作为可移动装置，使得塑料金属管能够以多个角度执行旋转和移动，并且延伸到用于连接的保持管中。 通过保持管内部的锁定装置，可以通过缩回来调节塑料金属管，从而提高监视器支撑架的灵活性，并使整个结构能够移动到任何角度并达到期望的位置，从而 以实现3D多角度的变化，并且有助于在遵循人体工程学的观看时增加舒适度。 此外，当塑料金属管完全缩回到保持管中时，监视器可以被调节为水平地或垂直地嵌入到由保持管附接的物体中以便收集，从而节省空间。

公开(公告)号：US08817914B2

公开(公告)日：2014-08-26

申请号：US13219563

申请日：2011-08-26

申请人： Amna Z. Shawwa ,  Chia-Jen Chang

发明人： Amna Z. Shawwa ,  Chia-Jen Chang

IPC分类号： H04L27/00 ,  G11C7/10 ,  H03K5/156

CPC分类号： G11C7/1084 ,  H03K5/1565

摘要： A receiver circuit. A receiving stage is coupled to a first supply voltage and an input signal, and operative to generate a first intermediate signal from the input signal based on the first supply voltage. A compensation stage is coupled to a second supply voltage and the first intermediate signal, and operative to generate a second intermediate signal by adjusting duty cycle of the first intermediate signal upon detecting changes in the first supply voltage to compensate for the changes in the first supply voltage. An outputting stage is coupled to the second supply voltage and operative to generate an output signal based on the second supply voltage upon receiving the second intermediate signal. A voltage of the output signal is adjusted to a level of the second supply voltage and the output signal has a 50% duty cycle.

摘要翻译： 接收机电路。 接收级耦合到第一电源电压和输入信号，并且可操作以基于第一电源电压从输入信号产生第一中间信号。 补偿级耦合到第二电源电压和第一中间信号，并且通过在检测到第一电源电压的变化以补偿第一电源的变化时调整第一中间信号的占空比来产生第二中间信号 电压。 输出级耦合到第二电源电压，并且用于在接收到第二中间信号时基于第二电源电压产生输出信号。 输出信号的电压被调整到第二电源电压的电平，并且输出信号具有50％的占空比。

公开(公告)号：US20130075728A1

公开(公告)日：2013-03-28

申请号：US13402997

申请日：2012-02-23

申请人： Chuan-Feng Liu ,  Chi-Ming Wu ,  Chia-Jen Chang

发明人： Chuan-Feng Liu ,  Chi-Ming Wu ,  Chia-Jen Chang

IPC分类号： H01L29/786

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/1251 ,  H01L29/41733

摘要： An array substrate includes scan lines and data lines defining pixel structures. Each pixel structure includes a first TFT, a second TFT and a pixel electrode. The first TFT includes a first gate connected to the scan line, a first source disposed above and partially overlapping the first gate, and a first drain disposed above the first gate. An end of the first source is connected to the data line. The first drain has at least one first concavity in which the first source is disposed partially. The second TFT includes a second gate connected to the scan line, a second source disposed above the second gate and connected to the first drain, and a second drain disposed above and partially overlapping the second gate. The second source has at least one second concavity in which the second drain is disposed partially. The pixel electrode connects to the second drain.

摘要翻译： 阵列基板包括限定像素结构的扫描线和数据线。 每个像素结构包括第一TFT，第二TFT和像素电极。 第一TFT包括连接到扫描线的第一栅极，设置在第一栅极上方并部分地与第一栅极重叠的第一源极和设置在第一栅极上方的第一漏极。 第一个源的一端连接到数据线。 第一漏极具有至少一个第一凹部，其中第一源部分地设置。 第二TFT包括连接到扫描线的第二栅极，设置在第二栅极上方并连接到第一漏极的第二源极，以及设置在第二栅极上方并部分地与第二栅极重叠的第二漏极。 第二源具有至少一个第二凹部，其中第二漏极部分地设置。 像素电极连接到第二漏极。

公开(公告)号：US20110176376A1

公开(公告)日：2011-07-21

申请号：US13073991

申请日：2011-03-28

申请人： Chia-Jen Chang ,  Phat Truong

发明人： Chia-Jen Chang ,  Phat Truong

IPC分类号： G11C8/18

CPC分类号： G11C8/06 ,  G11C7/1072

摘要： A synchronous memory array includes: a command receiver, for receiving a command signal; an address receiver, for receiving an address signal corresponding to the command signal where the address signal is delayed with respect to the command signal and the address receiver is initially in an off state; and a decoder, coupled to the command receiver and the address receiver, for decoding the command signal to selectively generate a receiver enable signal for turning on the address receiver.

摘要翻译： 同步存储器阵列包括：命令接收器，用于接收命令信号; 地址接收器，用于接收对应于地址信号相对于命令信号延迟的命令信号的地址信号，并且地址接收器最初处于关闭状态; 以及耦合到命令接收器和地址接收器的解码器，用于对命令信号进行解码以选择性地产生用于接通地址接收器的接收器使能信号。

公开(公告)号：US20100244940A1

公开(公告)日：2010-09-30

申请号：US12413596

申请日：2009-03-29

申请人： Phat Truong ,  Pauline Mai ,  Chia-Jen Chang

发明人： Phat Truong ,  Pauline Mai ,  Chia-Jen Chang

IPC分类号： G05F5/02

CPC分类号： H03K19/00384

摘要： An integrated circuit includes: a pre-driver stage, coupled to an external supply voltage, for controlling the final driver stage; a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; a compensation circuit, coupled to the pre-driver stage, for providing a bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage; and a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing a bias voltage as an input to the compensation circuit.

摘要翻译： 集成电路包括：预驱动器级，耦合到外部电源电压，用于控制最终的驱动级; 耦合到预驱动器级和外部电源电压的最终驱动器级，用于提供输出电压; 耦合到预驱动器级的补偿电路，用于向前驱动器级提供偏置电压，其补偿外部电源电压的变化，以控制通过前驱动器级的电流; 以及耦合到外部电源电压和补偿电路的偏置电路，用于提供偏置电压作为对补偿电路的输入。

公开(公告)号：US06970392B1

公开(公告)日：2005-11-29

申请号：US09895306

申请日：2001-06-29

申请人： Johnie Au ,  Chia Jen Chang ,  Parinda Mekara

发明人： Johnie Au ,  Chia Jen Chang ,  Parinda Mekara

IPC分类号： G06F5/14 ,  G11C7/00

CPC分类号： G06F5/14 ,  G06F2205/126

摘要： A state machine comprising a first input receiving a first read clock, a second input receiving a first write clock, a third input receiving a first programmable Almost Full look-ahead signal, a fourth input receiving a second read clock, a fifth input receiving a second write clock, and a sixth input receiving a second programmable Almost Full look-ahead signal is disclosed. The state machine manipulates the inputs to produce an output signal representing an Almost Full output flag that is at a first logic state when a FIFO is Almost Full and is at a second logic state when the FIFO is Not Almost Full.

摘要翻译： 一种状态机，包括接收第一读取时钟的第一输入，接收第一写入时钟的第二输入，接收第一可编程的全部前置信号的第三输入，接收第二读取时钟的第四输入，接收第一读取时钟的第五输入 第二写入时钟以及第六输入端接收第二可编程的近似全视场信号。 状态机操纵输入以产生表示几乎全输出标志的输出信号，当FIFO几乎满时处于第一逻辑状态，并且当FIFO不满足时处于第二逻辑状态。

公开(公告)号：US5898626A

公开(公告)日：1999-04-27

申请号：US879208

申请日：1997-06-19

申请人： Paul M-Bhor Chiang ,  Hung-Mao Lin ,  Chia-Jen Chang

发明人： Paul M-Bhor Chiang ,  Hung-Mao Lin ,  Chia-Jen Chang

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/83 ,  G11C29/84

摘要： Circuit, method, and system aspects for achieving redundancy circuitry programming in semiconductor memory are provided. Through these aspects, utilization of a circuit including a logic mechanism for receiving an enable signal and an address signal, a switching mechanism coupled to the logic mechanism for controlling delivery of the address signal, and a fuse mechanism coupled to the logic mechanism for allowing selective address programming responsive to the address signal in order to produce a desired logic level for a redundant address output signal occurs to form an address programming circuit. Further, selective input of an enable signal to the address programming circuit provides control of the address programming circuit to produce a desired logic level output. Additionally, integration of a plurality of the address programming circuits to form a redundancy programming circuit is achieved with each address programming circuit corresponding to one bit of an input address signal.

摘要翻译： 提供了用于实现半导体存储器中的冗余电路编程的电路，方法和系统方面。 通过这些方面，利用包括用于接收使能信号和地址信号的逻辑机构的电路，耦合到用于控制地址信号的传送的逻辑机构的开关机构，以及耦合到逻辑机构的熔丝机构， 发生响应于地址信号的地址编程以产生用于冗余地址输出信号的期望逻辑电平以形成地址编程电路。 此外，使能信号向地址编程电路的选择性输入提供地址编程电路的控制以产生期望的逻辑电平输出。 此外，利用对应于输入地址信号的一位的每个地址编程电路来实现多个地址编程电路的集成以形成冗余编程电路。