公开(公告)号：US20090108417A1

公开(公告)日：2009-04-30

申请号：US11931284

申请日：2007-10-31

申请人： Chikara Azuma

发明人： Chikara Azuma

IPC分类号： H01L23/528 ,  H01L21/4763

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/00

摘要： A multi-layered integrated circuit chip package comprises a void layer that includes at least one void. The multi-layered integrated circuit chip package also includes an insulation layer that electrically insulates the void layer from a trace layer. At least one trace resides in the trace layer. The trace having a length in which a first section thereof is located an overlying relation to the at least one void, wherein the first section overlying the void has a width different from an adjacent section of the trace located on at least one opposing side of the void such that impedance mismatches and signal reflections along the trace are mitigated.

摘要翻译： 一种多层集成电路芯片封装，其包括至少一个空隙的空隙层。 多层集成电路芯片封装还包括使空隙层与迹线层电绝缘的绝缘层。 轨迹图层中至少有一个轨迹。 所述迹线具有其第一部分与所述至少一个空隙相重叠的长度，其中覆盖所述空隙的所述第一部分的宽度不同于位于所述至少一个空隙的至少一个相对侧上的所述迹线的相邻部分 使得沿着迹线的阻抗失配和信号反射得到缓解。

公开(公告)号：US06225703B1

公开(公告)日：2001-05-01

申请号：US09350868

申请日：1999-07-09

申请人： Norito Umehara ,  Chikara Azuma ,  Akira Karashima

发明人： Norito Umehara ,  Chikara Azuma ,  Akira Karashima

IPC分类号： H01L2328

CPC分类号： H01L23/16 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The purpose of the present invention is to reduce the warpage of the semiconductor package caused by thermal contraction. According to the present invention, semiconductor device (9) has plate-shaped member (7) which is positioned on a surface of semiconductor chip (1) and is sealed together with semiconductor chip (1) with molding resin (8). Said plate-shaped member (7) has a linear expansion coefficient that is less than the linear expansion coefficient of the aforementioned molding resin. By placing a plate-shaped member with a small linear expansion coefficient on semiconductor chip (1), it is possible to reduce the thermal contraction on the upper side of the semiconductor chip. Also, the presence of the plate-shaped member on the semiconductor chip leads to substantial reduction in the thickness of the molding resin on the semiconductor chip. The pulling force due to contraction of the molding resin that leads to warping is proportional to the thickness of the molding resin. Consequently, by using semiconductor device (9) of the present invention that contains the aforementioned plate-shaped member, it is possible to reduce the warpage of the package to a very low level.

摘要翻译： 本发明的目的是减少由热收缩引起的半导体封装的翘曲。 根据本发明，半导体器件（9）具有位于半导体芯片（1）的表面上并与半导体芯片（1）一起用模塑树脂（8）密封的板状部件（7）。 所述板状部件（7）的线膨胀系数小于上述成形树脂的线膨胀系数。 通过在半导体芯片（1）上放置具有小线性膨胀系数的板状构件，可以减小半导体芯片的上侧的热收缩。 此外，半导体芯片上的板状构件的存在导致半导体芯片上的模塑树脂的厚度显着降低。 由于模制树脂的收缩导致翘曲的拉力与模制树脂的厚度成比例。 因此，通过使用包含上述板状部件的本发明的半导体装置（9），能够将包装的翘曲度降低到非常低的水平。