公开(公告)号：US20090161275A1

公开(公告)日：2009-06-25

申请号：US12122719

申请日：2008-05-18

Applicant: Kun-Tai Wu ,  Chin-Chieh Chao ,  Ching-Ching Chi

Inventor： Kun-Tai Wu ,  Chin-Chieh Chao ,  Ching-Ching Chi

IPC: H02H3/20

CPC classification number: H03F3/45475 ,  H01L27/0251 ,  H03F1/52 ,  H03F2200/444 ,  H03F2203/45136 ,  H03F2203/45594

Abstract: An integrated controlling chip includes a signal processing unit, a resistance unit and an electrostatic discharge protection circuit. The signal processing unit includes an input port. The resistance unit includes a first node coupled to a signal pin of the integrated controlling chip, and includes a second node coupled to the input port of the signal processing unit. The electrostatic discharge protection circuit includes a node coupled between the first node of the resistance unit and the signal pin of the integrated controlling chip.

Abstract translation: 集成控制芯片包括信号处理单元，电阻单元和静电放电保护电路。 信号处理单元包括输入端口。 电阻单元包括耦合到集成控制芯片的信号引脚的第一节点，并且包括耦合到信号处理单元的输入端口的第二节点。 静电放电保护电路包括耦合在电阻单元的第一节点和集成控制芯片的信号引脚之间的节点。

公开(公告)号：US5945851A

公开(公告)日：1999-08-31

申请号：US987035

申请日：1997-12-09

Applicant: Chien-Cheng Tu ,  Ching-Ching Chi

Inventor： Chien-Cheng Tu ,  Ching-Ching Chi

IPC: H03K5/24 ,  H03M1/74 ,  H03K5/22

CPC classification number: H03K5/2481 ,  H03M1/747

Abstract: A current source apparatus with bias switches, applied in digital-to-analog converters, is disclosed. The current compliance and settling time performances can be promoted via improving the structure of the bias circuit and making the MOS transistors operate in the saturation region, without increasing the dimensions of the MOS transistors.

Abstract translation: 公开了一种应用于数模转换器的偏置开关电流源装置。 通过改善偏置电路的结构并使MOS晶体管在饱和区域中工作，而不增加MOS晶体管的尺寸，可以促进电流顺应性和稳定时间性能。

公开(公告)号：US5598375A

公开(公告)日：1997-01-28

申请号：US494275

申请日：1995-06-23

Applicant: Jyh-Ren Yang ,  Ching-Ching Chi ,  Tien-Yu Wu

Inventor： Jyh-Ren Yang ,  Ching-Ching Chi ,  Tien-Yu Wu

IPC: G11C8/10 ,  G11C11/418 ,  G11C8/00

CPC classification number: G11C8/10 ,  G11C11/418

Abstract: An address decoder having non-overlapping word line enable is disclosed having a dynamic logic gate-based decoding section. The decoder includes a deadtime signal generator that produces a pulse at the rising edge of every input clock cycle. The decoder further includes a transmission gate responsive to the deadtime signal for selectively passing the decoder section output signal to a latch. The decoder further includes a NOR logic having an output for coupling to a memory word line which is gated by the deadtime signal to disable the output while the transmission gate passes the decoder output to the latch. When the deadtime pulse transitions to a low state, the latch captures the decoder output signal and enables the output of the NOR gate.

Abstract translation: 公开了一种具有非重叠字线使能的地址解码器，其具有基于动态逻辑门的解码部分。 解码器包括在每个输入时钟周期的上升沿产生脉冲的死区时间信号发生器。 解码器还包括响应于死区时间信号的传输门，用于选择性地将解码器部分输出信号传递到锁存器。 解码器还包括NOR逻辑，其具有用于耦合到由死区时间信号选通的存储器字线的输出，以在传输门将解码器输出通过锁存器时禁止输出。 当死区脉冲转变到低电平状态时，锁存器捕获解码器输出信号并使能NOR门的输出。

公开(公告)号：US07199778B2

公开(公告)日：2007-04-03

申请号：US10372866

申请日：2003-02-24

Applicant: Ching-Ching Chi ,  Hsiao-Yi Lin

Inventor： Ching-Ching Chi ,  Hsiao-Yi Lin

IPC: G09G3/36 ,  H03L7/00

CPC classification number: G09G3/3688 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/08 ,  G09G2310/027 ,  G09G2320/0247

Abstract: A switching signal generator of an active matrix display is disclosed. The switching signal generator includes at least one delay device connected to the switches of the active matrix display. The delay device consists of many delay units connected in series for receiving a source switching signal and correspondingly generating a plurality of target switching signals controlling the switches. There is a constant phase shift between any two successive target switching signals so that the switches are switched on one by one at regular intervals.

Abstract translation: 公开了一种有源矩阵显示器的切换信号发生器。 开关信号发生器包括连接到有源矩阵显示器的开关的至少一个延迟器件。 延迟装置包括许多串联连接的延迟单元，用于接收源极切换信号并相应地产生控制开关的多个目标切换信号。 在任意两个连续的目标切换信号之间存在恒定的相移，使得开关以规则的间隔逐个切换。