公开(公告)号：US20070161178A1

公开(公告)日：2007-07-12

申请号：US11308680

申请日：2006-04-21

申请人： Heng-Yuan Lee ,  Ching-Yuan Ho ,  Lurng-Shehng Lee ,  Chieh-Shuo Liang

发明人： Heng-Yuan Lee ,  Ching-Yuan Ho ,  Lurng-Shehng Lee ,  Chieh-Shuo Liang

IPC分类号： H01L21/8242

CPC分类号： H01L28/40

摘要： A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

摘要翻译： 提供了至少包括基板，圆柱形底电极，结构层，顶电极和电容器介电层的圆柱形电容器。 基板有几个插头。 圆柱形底部电极设置在基板上并电连接到相应的插头。 结构层围绕每个圆柱形底部电极的周边。 围绕两个相对的圆柱形底部电极的结构层不会相互接触，而围绕两个相邻的圆柱形底部电极的结构层彼此接触。 此外，顶部电极覆盖相应的圆柱形底部电极，并且电容器介电层设置在每个顶部电极和相应的圆柱形底部电极之间。 由于结构层，提高了整个圆柱形电容器的机械强度，并且可以增加电容器的密度。

公开(公告)号：USD660110S1

公开(公告)日：2012-05-22

申请号：US29371603

申请日：2011-05-10

申请人： Chen Hao Yang ,  Ching-Yuan Ho

设计人： Chen Hao Yang ,  Ching-Yuan Ho

公开(公告)号：US07332393B2

公开(公告)日：2008-02-19

申请号：US11308680

申请日：2006-04-21

申请人： Heng-Yuan Lee ,  Ching-Yuan Ho ,  Lurng-Shehng Lee ,  Chieh-Shuo Liang

发明人： Heng-Yuan Lee ,  Ching-Yuan Ho ,  Lurng-Shehng Lee ,  Chieh-Shuo Liang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/40

摘要： A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

摘要翻译： 提供了至少包括基板，圆柱形底电极，结构层，顶电极和电容器介电层的圆柱形电容器。 基板有几个插头。 圆柱形底部电极设置在基板上并电连接到相应的插头。 结构层围绕每个圆柱形底部电极的周边。 围绕两个相对的圆柱形底部电极的结构层不会相互接触，而围绕两个相邻的圆柱形底部电极的结构层彼此接触。 此外，顶部电极覆盖相应的圆柱形底部电极，并且电容器介电层设置在每个顶部电极和相应的圆柱形底部电极之间。 由于结构层，提高了整个圆柱形电容器的机械强度，并且可以增加电容器的密度。

公开(公告)号：US6146995A

公开(公告)日：2000-11-14

申请号：US985698

申请日：1997-12-05

申请人： Ching-Yuan Ho

发明人： Ching-Yuan Ho

IPC分类号： H01L21/768 ,  H01L21/4763 ,  H01L21/302

CPC分类号： H01L21/76819 ,  H01L21/7684

摘要： A method for forming interconnection plugs comprising the steps of providing a substrate having a dielectric layer formed thereon, wherein an opening exposing a pad area for connection with other structures is also formed in the dielectric layer. Next, a glue layer is formed over the pad area and the dielectric sidewalls of the opening. Subsequently, plug material is deposited into the opening forming a plug layer. This is followed by etching back the plug layer to return the plug material inside the opening to a level below the height of the dielectric layer. Then, a selective etching method having a high selectivity ratio between the dielectric layer and the plug layer is used to etch the dielectric layer. Finally, the dielectric layer and the plug layer are etched to almost the same level of height. The characteristic of this invention is the utilization of the higher etching r!ate of dielectric material with respect to the plug material so that the dielectric layer is etched back to the same level of height as the plug layer. Hence, the formation of recesses on the plug surface and the surface of subsequently deposited metallic layer is avoided.

摘要翻译： 一种用于形成互连插头的方法，包括以下步骤：提供其上形成有电介质层的衬底，其中在电介质层中还形成露出用于与其它结构连接的焊盘区域的开口。 接下来，在焊盘区域和开口的电介质侧壁上形成胶层。 随后，塞子材料沉积到形成塞子层的开口中。 接下来是将插塞层回蚀以使开口内的插塞材料返回至低于介电层高度的水平。 然后，使用在电介质层和插塞层之间具有高选择率的选择性蚀刻方法来蚀刻电介质层。 最后，电介质层和插塞层被蚀刻到几乎相同的高度。 本发明的特征是利用电介质材料相对于插塞材料的较高蚀刻速率，使得电介质层被回蚀到与插塞层相同的高度水平。 因此，避免了插头表面上的凹陷的形成和随后沉积的金属层的表面。

公开(公告)号：US20070155074A1

公开(公告)日：2007-07-05

申请号：US11408940

申请日：2006-04-24

申请人： Ching-Yuan Ho ,  Chen-Hsin Lien

发明人： Ching-Yuan Ho ,  Chen-Hsin Lien

IPC分类号： H01L21/8234

CPC分类号： H01L21/28035 ,  H01L21/28114 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device to lower source/drain sheet resistance is provided. A dielectric layer with a plurality of contact windows is formed on a semiconductor device. Next, selective epitaxial growth (SEG) is implemented, and then a metal layer is sputtered. After that, a silicide is formed by heat treatment. In another embodiment, selective epitaxial growth is implemented first, and then a dielectric layer with a plurality of contact windows is formed. Then, a metal layer is sputtered, and a silicide is then formed by heat treatment. Since the silicide is formed by way of SEG, the silicon substrate will not be consumed during the process of forming the silicide, and the depth of the junction region is maintained, and the source/drain sheet resistance is lowered.

摘要翻译： 提供一种制造半导体器件以降低源/漏片电阻的方法。 在半导体器件上形成具有多个接触窗口的电介质层。 接下来，实施选择性外延生长（SEG），然后溅射金属层。 之后，通过热处理形成硅化物。 在另一个实施例中，首先实现选择性外延生长，然后形成具有多个接触窗口的电介质层。 然后，溅射金属层，然后通过热处理形成硅化物。 由于硅化物通过SEG形成，硅衬底在形成硅化物的过程中不会被消耗，并且保持接合区域的深度，并且降低了源/漏片电阻。

公开(公告)号：US20060097298A1

公开(公告)日：2006-05-11

申请号：US11119880

申请日：2005-05-03

申请人： Ching-Yuan Ho

发明人： Ching-Yuan Ho

IPC分类号： H01L29/94

CPC分类号： G11C11/16 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic random access memory with reduced currents in a bit line and a manufacturing method thereof. In one embodiment, the memory includes a bottom electrode, a first dielectric layer on the bottom electrode, a via in the first dielectric layer, a magnetic tunnel junction (MTJ) element that is aligned with and formed on a via, and a metal layer that is formed on and in contact with an MTJ element. In another embodiment, a second dielectric layer is formed on the first dielectric layer, and a metal layer is formed on and in contact with an MTJ element and the second dielectric layer. These designs can protect the MTJ element from damage during the etching process. Hence it increases the stability and the yield rate during the manufacturing process. Furthermore, the designs can reduce the current requirements of running magnetic cells, thereby reducing power consumption.

摘要翻译： 一种位线中电流降低的磁性随机存取存储器及其制造方法。 在一个实施例中，存储器包括底部电极，底部电极上的第一介电层，第一介电层中的通孔，与通孔对准并形成在通孔上的磁性隧道结（MTJ）元件，以及金属层 其形成在MTJ元件上并与其接触。 在另一个实施例中，在第一电介质层上形成第二电介质层，并且金属层形成在MTJ元件和第二介电层上并与之接触。 这些设计可以保护MTJ元件免受蚀刻过程中的损坏。 因此，在制造过程中增加了稳定性和成品率。 此外，这些设计可以减少运行磁性电池的电流要求，从而降低功耗。

公开(公告)号：US07473641B2

公开(公告)日：2009-01-06

申请号：US11489630

申请日：2006-07-20

申请人： Ching-Yuan Ho ,  Yung-Hsiang Chen

发明人： Ching-Yuan Ho ,  Yung-Hsiang Chen

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L43/12

摘要： A method for manufacturing a semiconductor device is provided. First, a first metal conductive line is formed, and then a semiconductor device is formed on the first metal conductive line. A dielectric layer is formed on the semiconductor device. A contact window is formed at a position in the dielectric layer corresponding to the first metal conductive line. Then, a metal plug is formed in the contact window. The metal plug is used as a mask for etching the semiconductor device, such that the etched semiconductor device takes the form of a shape corresponding to the metal plug. Through the manufacturing method, the semiconductor device is formed according to the shape of the metal plug and is completely aligned with the metal plug.

摘要翻译： 提供一种制造半导体器件的方法。 首先，形成第一金属导线，然后在第一金属导线上形成半导体器件。 在半导体器件上形成介电层。 在对应于第一金属导线的电介质层中的一个位置处形成接触窗口。 然后，在接触窗中形成金属塞。 金属插塞用作蚀刻半导体器件的掩模，使得蚀刻的半导体器件采取与金属插塞相对应的形状。 通过制造方法，根据金属插头的形状形成半导体器件，并且与金属插塞完全对准。

公开(公告)号：US20100093142A1

公开(公告)日：2010-04-15

申请号：US12248049

申请日：2008-10-09

申请人： Ching-Yuan Ho ,  Hirotake Fujita ,  Po-Jui Chiang

发明人： Ching-Yuan Ho ,  Hirotake Fujita ,  Po-Jui Chiang

IPC分类号： H01L21/336 ,  H01L21/314

CPC分类号： H01L27/11521

摘要： A method of fabricating a device is described. A substrate having at least two isolation structures is provided. A first oxide layer and a first conductive layer are sequentially formed on the substrate between the isolation structures. A first nitridation process is performed to form a first nitride layer on the surface of the first conductive layer and a first oxynitride layer on the surface of the isolation structures. A second oxide layer is formed on the first nitride layer and first oxynitride layer. A densification process is performed to oxidize the first oxynitride layer on the surface of the isolation structures. A second nitride layer and a third oxide layer are sequentially formed on the second oxide layer. A second nitridation process is performed to form a third nitride layer on the surface of the third oxide layer. A second conductive layer is formed on the third nitride layer.

摘要翻译： 描述了一种制造装置的方法。 提供具有至少两个隔离结构的衬底。 在隔离结构之间的衬底上依次形成第一氧化物层和第一导电层。 进行第一氮化处理以在第一导电层的表面上形成第一氮化物层，在隔离结构的表面上形成第一氮氧化物层。 在第一氮化物层和第一氮氧化物层上形成第二氧化物层。 进行致密化处理以氧化隔离结构的表面上的第一氧氮化物层。 在第二氧化物层上依次形成第二氮化物层和第三氧化物层。 进行第二次氮化处理以在第三氧化物层的表面上形成第三氮化物层。 在第三氮化物层上形成第二导电层。

公开(公告)号：US07465664B2

公开(公告)日：2008-12-16

申请号：US11408940

申请日：2006-04-24

申请人： Ching-Yuan Ho ,  Chen-Hsin Lien

发明人： Ching-Yuan Ho ,  Chen-Hsin Lien

IPC分类号： H01L21/44 ,  H01L23/52

CPC分类号： H01L21/28035 ,  H01L21/28114 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device to lower source/drain sheet resistance is provided. A dielectric layer with a plurality of contact windows is formed on a semiconductor device. Next, selective epitaxial growth (SEG) is implemented, and then a metal layer is sputtered. After that, a silicide is formed by heat treatment. In another embodiment, selective epitaxial growth is implemented first, and then a dielectric layer with a plurality of contact windows is formed. Then, a metal layer is sputtered, and a silicide is then formed by heat treatment. Since the silicide is formed by way of SEG, the silicon substrate will not be consumed during the process of forming the silicide, and the depth of the junction region is maintained, and the source/drain sheet resistance is lowered.

摘要翻译： 提供一种制造半导体器件以降低源/漏片电阻的方法。 在半导体器件上形成具有多个接触窗口的电介质层。 接下来，实施选择性外延生长（SEG），然后溅射金属层。 之后，通过热处理形成硅化物。 在另一个实施例中，首先实现选择性外延生长，然后形成具有多个接触窗口的电介质层。 然后，溅射金属层，然后通过热处理形成硅化物。 由于硅化物通过SEG形成，硅衬底在形成硅化物的过程中不会被消耗，并且保持接合区域的深度，并且降低了源/漏片电阻。

公开(公告)号：US20080094776A1

公开(公告)日：2008-04-24

申请号：US11960726

申请日：2007-12-20

申请人： Heng-Yuan Lee ,  Ching-Yuan Ho ,  Lurng-Shehng Lee ,  Chieh-Shuo Liang

发明人： Heng-Yuan Lee ,  Ching-Yuan Ho ,  Lurng-Shehng Lee ,  Chieh-Shuo Liang

IPC分类号： H01G4/00

CPC分类号： H01L28/40

摘要： A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.

摘要翻译： 提供了至少包括基板，圆柱形底电极，结构层，顶电极和电容器介电层的圆柱形电容器。 基板有几个插头。 圆柱形底部电极设置在基板上并电连接到相应的插头。 结构层围绕每个圆柱形底部电极的周边。 围绕两个相对的圆柱形底部电极的结构层不会相互接触，而围绕两个相邻的圆柱形底部电极的结构层彼此接触。 此外，顶部电极覆盖相应的圆柱形底部电极，并且电容器介电层设置在每个顶部电极和相应的圆柱形底部电极之间。 由于结构层，提高了整个圆柱形电容器的机械强度，并且可以增加电容器的密度。