公开(公告)号：US08724420B2

公开(公告)日：2014-05-13

申请号：US13105382

申请日：2011-05-11

Applicant: Chiting Cheng ,  Chung-Cheng Chou ,  Tsung-yung Jonathan Chang

Inventor： Chiting Cheng ,  Chung-Cheng Chou ,  Tsung-yung Jonathan Chang

IPC: G11C11/413

CPC classification number: G11C11/419 ,  G11C11/41 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028

Abstract: An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.

Abstract translation: SRAM写入辅助装置包括定时器单元和分压器。 分压器单元被配置为将电压电位分压到较低电平。 在写入操作中，分压器的输出连接到存储单元。 定时器单元被配置为产生具有与施加到存储芯片的电压电位成反比的宽度的脉冲。 此外，定时器单元控制将来自分压器的输出的较低电压施加到存储单元的周期。 此外，可以使用外部电平和定时可编程信号来进一步调整分压器的比例和来自定时器单元的脉冲宽度。 通过采用SRAM写入辅助装置，存储器芯片可以执行可靠且快速的写入操作。

公开(公告)号：US20130121055A1

公开(公告)日：2013-05-16

申请号：US13297296

申请日：2011-11-16

Applicant: Shu Cheng HUANG ,  Hsin-Hsin KO ,  Jung-Hsuan CHEN ,  Chiting CHENG

Inventor： Shu Cheng HUANG ,  Hsin-Hsin KO ,  Jung-Hsuan CHEN ,  Chiting CHENG

IPC: G11C8/08 ,  H01L21/768 ,  G11C5/06

CPC classification number: G11C11/413

Abstract: A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques and enables the formation of all word lines from a single metal layer which, in turn, enables overlying and underlying metal levels to be used for other features such as signal lines for word line decoders. A power mesh is formed using multiple metal layers and the formation of all the word lines from a single metal layer enables VDD and VSS power lines that are formed from an overlying layer to extend orthogonal to the cell direction and include wider widths reducing metal line resistance and increasing the deliverable power.

Abstract translation: 提供了适用于诸如SRAM，静态随机存取存储器件等RAM装置的字线驱动单元。 字线驱动器单元与双模式处理技术兼容，并且能够从单个金属层形成所有字线，这又可以使覆盖和下层金属电平用于其他特征，例如用于字线解码器的信号线 。 使用多个金属层形成功率网，并且从单个金属层形成所有字线使得由上层形成的VDD和VSS电源线能够垂直于电池方向延伸并且包括较宽的宽度，从而减小金属线路电阻 并增加可交付的能力。

公开(公告)号：US20130069236A1

公开(公告)日：2013-03-21

申请号：US13238294

申请日：2011-09-21

Applicant: Jung-Hsuan Chen ,  May Chang ,  Chiting Cheng ,  Li-Chun Tien

Inventor： Jung-Hsuan Chen ,  May Chang ,  Chiting Cheng ,  Li-Chun Tien

IPC: H01L23/52 ,  G06F17/50

CPC classification number: H01L27/0207 ,  H01L2027/11859

Abstract: Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.

Abstract translation: 提供半导体器件单元，用于形成半导体器件单元的方法和用于半导体器件单元的布局样式。 器件单元可以是整个集成电路中使用的重复单元。 布局样式利用多晶硅级别的无多晶硅的区域，并且其可以容纳其中或其中的导电引线。 导电引线由通常用于触点或通孔的材料形成，并且设置在将器件单元彼此耦合的第一金属互连级之下。 下面的局部导电引线可以形成下面的信号线，允许额外的功率网线被包括在可以容纳在器件单元内并根据金属轨道设计间隔规则的有限数量的金属轨道内。

公开(公告)号：US09064550B2

公开(公告)日：2015-06-23

申请号：US13279375

申请日：2011-10-24

Applicant: Jonathan Tsung-Yung Chang ,  Chiting Cheng ,  Chien-Kuo Su ,  Chung-Cheng Chou ,  Jack Liu

Inventor： Jonathan Tsung-Yung Chang ,  Chiting Cheng ,  Chien-Kuo Su ,  Chung-Cheng Chou ,  Jack Liu

IPC: G11C11/00 ,  G11C8/08 ,  G11C11/418

CPC classification number: G11C8/08 ,  G11C11/418

Abstract: A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.

Abstract translation: 数字存储器的位单元（例如静态随机存取存储器（SRAM））上的存储器访问操作通过减少字线控制电压来进行辅助，用于读取和提升其用于写入，从而提高数据完整性。 位单元具有交叉耦合的反相器，用于经由位线连接通过由字线控制的通过栅极晶体管来存储和取回逻辑状态。 控制通过栅极晶体管的字线信号的电平从第一电压值移位到较高的第二电压值，以开始存储器访问周期。 在访问周期期间，字线信号的电平从第二电压值移位到小于第二电压值的第三电压值。 在访问周期期间，字线信号保持在第三电压值一段时间间隔。

公开(公告)号：US09025356B2

公开(公告)日：2015-05-05

申请号：US13221081

申请日：2011-08-30

Applicant: Hsiao-Wen Lu ,  Wei-Jer Hsieh ,  Chiting Cheng ,  Chung-Cheng Chou ,  Jonathan Tsung-Yung Chang

Inventor： Hsiao-Wen Lu ,  Wei-Jer Hsieh ,  Chiting Cheng ,  Chung-Cheng Chou ,  Jonathan Tsung-Yung Chang

IPC: G11C5/06 ,  G11C7/10 ,  G11C11/00 ,  G11C11/413

CPC classification number: G11C5/063 ,  G11C11/413 ,  Y10T307/445

Abstract: The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal source, and coupling the more distant subset to the signal through a fly-over conductor that bypasses the subset that is nearer to the signal source. The technique is applicable to subsets of bit cells in a random access memory (SRAM) coupled to a given word line, or to word line decoder gates coupled sequentially to a strobe signal, as well as other circuits wherein load devices selectable as a group can be divided into subsets by proximity to the signal source. In an SRAM layout with multiple levels, different metal deposition layers carry the conductor legs between the load devices versus the fly-over conductor bypassing the nearer subset.

Abstract translation: 通过分离距离信号源更远的负载装置的子集，并通过飞越导体将更远的子集耦合到信号，改善了通过沿导体顺序耦合的多个负载装置的信号的传播延迟， 绕过更靠近信号源的子集。 该技术适用于耦合到给定字线的随机存取存储器（SRAM）中的位单元的子集，或者适用于顺序耦合到选通信号的字线解码器门，以及其他可选择作为一组的负载装置的电路 通过靠近信号源将其划分为子集。 在具有多个级别的SRAM布局中，不同的金属沉积层承载负载装置之间的导体腿与绕过更近的子集的飞越导体。

公开(公告)号：US20130294181A1

公开(公告)日：2013-11-07

申请号：US13464489

申请日：2012-05-04

Applicant: Jonathan Tsung-Yung CHANG ,  Kun-Hsi LI ,  Chiting CHENG

Inventor： Jonathan Tsung-Yung CHANG ,  Kun-Hsi LI ,  Chiting CHENG

IPC: G11C7/00

CPC classification number: G11C11/419 ,  G11C11/41 ,  G11C29/028 ,  G11C29/56 ,  G11C2029/5002 ,  H01L21/78

Abstract: A semiconductor device includes at least one memory cell die. The at least one memory cell die includes a data storage unit. The at least one memory cell die includes at least one read assist enabling unit electrically connected to the data storage unit. The at least one read assist enabling unit configured to lower a voltage of a word line. The memory cell die also includes at least one write assist enabling unit electrically connected to the data storage unit. The at least one write assist enabling unit configured to supply a negative voltage to at least one of a bit line or a bit line bar.

Abstract translation: 半导体器件包括至少一个存储单元管芯。 所述至少一个存储单元管芯包括数据存储单元。 至少一个存储单元管芯包括电连接到数据存储单元的至少一个读辅助使能单元。 所述至少一个读辅助使能单元被配置为降低字线的电压。 存储单元管芯还包括电连接到数据存储单元的至少一个写辅助使能单元。 所述至少一个写入辅助使能单元被配置为向位线或位线条中的至少一个提供负电压。

公开(公告)号：US20120188838A1

公开(公告)日：2012-07-26

申请号：US13010039

申请日：2011-01-20

Applicant: Chiting Cheng ,  Hsiu-Feng Peng ,  Ming-Zhang Kuo ,  Chung-Cheng Chou

Inventor： Chiting Cheng ,  Hsiu-Feng Peng ,  Ming-Zhang Kuo ,  Chung-Cheng Chou

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C7/12 ,  G11C8/14 ,  G11C11/418 ,  G11C11/419

Abstract: A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits cells. A second word line segment driver is connected to the second plurality of bits cells. The first and second word line segment drivers are selectively operable for activating one of the first and second pluralities of bit cells at a time to the exclusion of the other plurality of bit cells. A shared sense amplifier is coupled to at least one of the first plurality of bit cells and at least one of the second plurality of bit cells. The shared sense amplifier is configured to receive signals from whichever of the one first or second bit cell is activated by its respective word line segment driver at a given time.

Abstract translation: 存储器包括一行比特单元，包括第一多个比特单元和第二多个比特单元。 第一字线段驱动器连接到第一多个位单元。 第二字线段驱动器连接到第二多个位单元。 第一和第二字线段驱动器被选择性地可操作用于一次激活第一和第二多个位单元之一以排除其他多个位单元。 共享读出放大器耦合到第一多个位单元和第二多个位单元中的至少一个位单元中的至少一个。 共享读出放大器被配置为在给定时间从其相应的字线段驱动器接收由一个第一或第二位单元中的哪一个激活的信号。

公开(公告)号：US08848461B2

公开(公告)日：2014-09-30

申请号：US13464489

申请日：2012-05-04

Applicant: Jonathan Tsung-Yung Chang ,  Kun-Hsi Li ,  Chiting Cheng

Inventor： Jonathan Tsung-Yung Chang ,  Kun-Hsi Li ,  Chiting Cheng

IPC: G11C7/22

CPC classification number: G11C11/419 ,  G11C11/41 ,  G11C29/028 ,  G11C29/56 ,  G11C2029/5002 ,  H01L21/78

Abstract: A semiconductor device includes at least one memory cell die. The at least one memory cell die includes a data storage unit. The at least one memory cell die includes at least one read assist enabling unit electrically connected to the data storage unit. The at least one read assist enabling unit configured to lower a voltage of a word line. The memory cell die also includes at least one write assist enabling unit electrically connected to the data storage unit. The at least one write assist enabling unit configured to supply a negative voltage to at least one of a bit line or a bit line bar.

Abstract translation: 半导体器件包括至少一个存储单元管芯。 至少一个存储单元管芯包括数据存储单元。 至少一个存储单元管芯包括电连接到数据存储单元的至少一个读辅助使能单元。 所述至少一个读辅助使能单元被配置为降低字线的电压。 存储单元管芯还包括电连接到数据存储单元的至少一个写辅助使能单元。 所述至少一个写入辅助使能单元被配置为向位线或位线条中的至少一个提供负电压。

公开(公告)号：US20130094307A1

公开(公告)日：2013-04-18

申请号：US13271353

申请日：2011-10-12

Applicant: Hong-Chen CHENG ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

Inventor： Hong-Chen CHENG ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C11/419

Abstract: In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.

Abstract translation: 在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和 响应于控制信号的待机模式。 位线偏置电路控制在处于睡眠模式时使位线浮动的电压。 用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。 连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

公开(公告)号：US20120307574A1

公开(公告)日：2012-12-06

申请号：US13149611

申请日：2011-05-31

Applicant: Chiting Cheng ,  Chung-Cheng Chou ,  Jonathan Tsung-Yung Chang

Inventor： Chiting Cheng ,  Chung-Cheng Chou ,  Jonathan Tsung-Yung Chang

IPC: G11C7/00

CPC classification number: G11C11/419

Abstract: A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures.

Abstract translation: SRAM读写辅助装置包括位线电压跟踪块，READ辅助定时器，READ辅助单元，WRITE辅助单元，WRITE控制单元。 位线电压跟踪块检测耦合到多个跟踪存储器单元的跟踪位线上的电压。 响应于跟踪位线上的电压降，READ辅助定时器产生READ辅助脉冲。 当READ辅助脉冲具有逻辑高电平状态时，激活的字线被下拉到较低的电压。 这样较低的电压有助于提高SRAM存储器电路的鲁棒性，以避免读取和写入故障。