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公开(公告)号：US20080209233A1
公开(公告)日：2008-08-28
申请号：US11678440
申请日：2007-02-23
IPC分类号： G06F1/00
CPC分类号： G06F9/4418
摘要： A technique of operating a processor subsystem masks interrupts to the processor subsystem during a power-down sequence of a processor of the processor subsystem. A boot vector for the processor of the processor subsystem is set. The boot vector provides an address associated with a saved processor state. A current state of the processor is saved to provide the saved processor state. The technique determines whether one or more first masked interrupts occurred during the saving of the current state of the processor. The processor that is to be powered-down is stopped when the one or more first masked interrupts did not occur during the saving of the current state of the processor. The technique also determines whether one or more second masked interrupts occurred following the saving of the current state of the processor. The processor is powered-down when the one or more second masked interrupts did not occur following the saving of the current state of the processor.
摘要翻译： 操作处理器子系统的技术在处理器子系统的处理器的掉电序列期间屏蔽处理器子系统的中断。 设置处理器子系统的处理器的引导向量。 引导向量提供与保存的处理器状态相关联的地址。 处理器的当前状态被保存以提供保存的处理器状态。 该技术确定在保存处理器的当前状态期间是否发生一个或多个第一屏蔽中断。 当在处理器的当前状态的保存期间没有发生一个或多个第一屏蔽中断时，将停止要被掉电的处理器。 该技术还确定在保存处理器的当前状态之后是否发生一个或多个第二屏蔽中断。 在保存处理器的当前状态之后，当一个或多个第二屏蔽中断没有发生时，处理器掉电。
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2.发明授权Techniques for operating a processor subsystem to service masked interrupts during a power-down sequence 有权用于在掉电序列期间操作处理器子系统以处理屏蔽的中断的技术公开(公告)号：US07779284B2
公开(公告)日：2010-08-17
申请号：US11678440
申请日：2007-02-23
CPC分类号： G06F9/4418
摘要： A technique of operating a processor subsystem masks interrupts to the processor subsystem during a power-down sequence of a processor of the processor subsystem. A boot vector for the processor of the processor subsystem is set. The boot vector provides an address associated with a saved processor state. A current state of the processor is saved to provide the saved processor state. The technique determines whether one or more first masked interrupts occurred during the saving of the current state of the processor. The processor that is to be powered-down is stopped when the one or more first masked interrupts did not occur during the saving of the current state of the processor. The technique also determines whether one or more second masked interrupts occurred following the saving of the current state of the processor. The processor is powered-down when the one or more second masked interrupts did not occur following the saving of the current state of the processor.
摘要翻译： 操作处理器子系统的技术在处理器子系统的处理器的掉电序列期间屏蔽处理器子系统的中断。 设置处理器子系统的处理器的引导向量。 引导向量提供与保存的处理器状态相关联的地址。 处理器的当前状态被保存以提供保存的处理器状态。 该技术确定在保存处理器的当前状态期间是否发生一个或多个第一屏蔽中断。 当在处理器的当前状态的保存期间没有发生一个或多个第一屏蔽中断时，将停止要被掉电的处理器。 该技术还确定在保存处理器的当前状态之后是否发生一个或多个第二屏蔽中断。 在保存处理器的当前状态之后，当一个或多个第二屏蔽中断没有发生时，处理器掉电。
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公开(公告)号：US07181188B2
公开(公告)日：2007-02-20
申请号：US10806498
申请日：2004-03-23
申请人： Mieu Van Vu , Christopher K. Chun , Arthur M. Goldberg , David J. Hayes , Charbel Khawand , Jianping Tao , John J. Vaglica
发明人： Mieu Van Vu , Christopher K. Chun , Arthur M. Goldberg , David J. Hayes , Charbel Khawand , Jianping Tao , John J. Vaglica
IPC分类号： H04B1/16
CPC分类号： H04W52/0277 , Y02D70/00
摘要： A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system (10) has power control circuitry (52) which may be used to control power usage in data processing system (10). Power mode select circuitry (84) may be used to select a power mode. Depending upon the power mode selected, power control circuitry (52) may use a cascaded approach to selecting which portions of data processing system (10) will be powered down, and thus how deeply data processing system (10) will be powered down.
摘要翻译： 提供一种用于进入低功率模式的方法和装置。 在一个实施例中，数据处理系统（10）具有功率控制电路（52），其可用于控制数据处理系统（10）中的功率使用。 电源模式选择电路（84）可用于选择电源模式。 根据所选择的功率模式，功率控制电路（52）可以使用级联的方法来选择数据处理系统（10）的哪些部分将被掉电，并且因此数据处理系统（10）将被断电多深。
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4.发明授权Multiplexing of digital signals at multiple supply voltages in an integrated circuit 有权在集成电路中以多个电源电压复用数字信号公开(公告)号：US06856173B1
公开(公告)日：2005-02-15
申请号：US10656051
申请日：2003-09-05
申请人： Christopher K. Chun
发明人： Christopher K. Chun
IPC分类号： H03K17/00 , H03K17/693 , H03K19/084
CPC分类号： H03K17/005 , H01L2924/0002 , H03K17/693 , H03K2217/0036 , H01L2924/00
摘要： An integrated circuit (10) includes a multiple voltage digital multiplexer circuit (30) for multiplexing digital signals provided at different supply voltage levels. In one form, the multiplexer (30) includes an analog multiplexer (32) for receiving the digital signals, a level shifter (40) coupled to the output of the analog multiplexer (32), and a supply voltage multiplexer (34) for providing one of various supply voltages used on the IC corresponding to the signals being multiplexed. A control circuit (38, 39) is used to control the input selection of the analog multiplexer (32) as well as the supply voltage multiplexer (34) for providing the correct supply voltage to the level shifter (40). This provides the ability to multiplex digital signals of differing voltage levels onto a single pad on the IC (10).
摘要翻译： 集成电路（10）包括用于复用以不同电源电压电平提供的数字信号的多电压数字多路复用器电路（30）。 在一种形式中，多路复用器（30）包括用于接收数字信号的模拟多路复用器（32），耦合到模拟多路复用器（32）的输出的电平转换器（40）和用于提供 对应于被复用的信号的IC上使用的各种电源电压之一。 控制电路（38,39）用于控制模拟多路复用器（32）的输入选择以及用于向电平转换器（40）提供正确的电源电压的电源电压多路复用器（34）。 这提供了将不同电压电平的数字信号复用到IC（10）上的单个焊盘上的能力。
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