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10 条记录 (耗时 0.016 秒)

    Method for fabricating memory
    1.
    发明授权
    Method for fabricating memory 有权
    制造记忆的方法

    公开(公告)号：US08927370B2

    公开(公告)日：2015-01-06

    申请号：US11459416

    申请日：2006-07-24

    申请人： Chun-Yuan Lo ,  Chun-Pei Wu

    发明人： Chun-Yuan Lo ,  Chun-Pei Wu

    IPC分类号： H01L21/8234 ,  H01L27/105 ,  H01L27/115

    CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

    摘要： A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.

    摘要翻译： 提供一种用于制造具有存储区域和周边区域的存储器的方法。 该方法包括在周边区域的基板上形成栅极绝缘层。 此后，在存储区域中形成第一导电层，随后在与第一导电层的侧面相邻的衬底中形成掩埋扩散区域。 然后在第一导电层之上形成栅极间电介质层，随后在栅极间电介质层上形成第二导电层。 随后在周边区域中的栅极绝缘层上形成晶体管栅极。

    MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20100202179A1

    公开(公告)日：2010-08-12

    申请号：US12366910

    申请日：2009-02-06

    申请人： Chun-Yuan Lo ,  Cheng-Ming Yih ,  Wen-Pin Lu

    发明人： Chun-Yuan Lo ,  Cheng-Ming Yih ,  Wen-Pin Lu

    IPC分类号： G11C5/02 ,  G11C7/02

    CPC分类号： H01L27/11519 ,  G11C5/005 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11565

    摘要： A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.

    摘要翻译： 提供存储器件。 存储器件包括衬底，多个字线，多个导电区域和至少屏蔽插头。 衬底具有存储区域和周边区域。 字线设置在基板上，并且至少设置在周边区域中并与字线相邻的虚拟字线。 导电区域分别设置在基板中和字线之间。 屏蔽插头位于基板上并且与虚拟字线相邻，并且在虚拟字线和字线之间，并且在伪字线周围没有自对准源极区域。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20080020525A1

    公开(公告)日：2008-01-24

    申请号：US11459416

    申请日：2006-07-24

    申请人： Chun-Yuan Lo ,  Chun-Pei Wu

    发明人： Chun-Yuan Lo ,  Chun-Pei Wu

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

    摘要： A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.

    摘要翻译： 提供一种用于制造具有存储区域和周边区域的存储器的方法。 该方法包括在周边区域的基板上形成栅极绝缘层。 此后，在存储区域中形成第一导电层，随后在与第一导电层的侧面相邻的衬底中形成掩埋扩散区域。 然后在第一导电层之上形成栅极间电介质层，随后在栅极间电介质层上形成第二导电层。 随后在周边区域中的栅极绝缘层上形成晶体管栅极。

    Memory device no common source region and method of fabricating the same
    5.
    发明授权
    Memory device no common source region and method of fabricating the same 有权
    存储器件没有共同的源极区域及其制造方法

    公开(公告)号：US08243489B2

    公开(公告)日：2012-08-14

    申请号：US13045153

    申请日：2011-03-10

    申请人： Chun-Yuan Lo ,  Cheng-Ming Yih ,  Wen-Pin Lu

    发明人： Chun-Yuan Lo ,  Cheng-Ming Yih ,  Wen-Pin Lu

    IPC分类号： G11C7/00

    CPC分类号： H01L27/11519 ,  G11C5/005 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11565

    摘要： A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.

    摘要翻译： 提供包括多个存储单元，多个字线，虚拟字线，至少第一导电区域和至少第一插头的存储器阵列。 每个字线耦合到相应的存储单元。 虚拟字线与多个字线的最外侧字线直接相邻。 第一导电区域仅设置在虚拟字线和最外侧字线之间。 第一个插头位于虚拟字线和最外面的字线之间。

    Memory device with shielding plugs adjacent to a dummy word line thereof
    6.
    发明授权
    Memory device with shielding plugs adjacent to a dummy word line thereof 有权
    具有与其虚拟字线相邻的屏蔽插头的存储器件

    公开(公告)号：US07924591B2

    公开(公告)日：2011-04-12

    申请号：US12366910

    申请日：2009-02-06

    申请人： Chun-Yuan Lo ,  Cheng-Ming Yih ,  Wen-Pin Lu

    发明人： Chun-Yuan Lo ,  Cheng-Ming Yih ,  Wen-Pin Lu

    IPC分类号： G11C7/02

    CPC分类号： H01L27/11519 ,  G11C5/005 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11565

    摘要： A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.

    摘要翻译： 提供存储器件。 存储器件包括衬底，多个字线，多个导电区域和至少屏蔽插头。 衬底具有存储区域和周边区域。 字线设置在基板上，并且至少设置在周边区域中并与字线相邻的虚拟字线。 导电区域分别设置在基板中和字线之间。 屏蔽插头位于基板上并且与虚拟字线相邻，并且在虚拟字线和字线之间，并且在伪字线周围没有自对准源极区域。

    Flash memory and memory cell programming method thereof
    7.
    发明授权
    Flash memory and memory cell programming method thereof 有权
    闪存及其存储单元编程方法

    公开(公告)号：US08526240B2

    公开(公告)日：2013-09-03

    申请号：US13211339

    申请日：2011-08-17

    申请人： Chun-Yuan Lo ,  Wein-Town Sun

    发明人： Chun-Yuan Lo ,  Wein-Town Sun

    IPC分类号： G11C16/06

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3459

    摘要： A programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of the memory cell. A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell. A flash memory is also provided.

    摘要翻译： 编程方法包括以下步骤。 将预设的编程电压施加到存储器单元以对存储器单元进行编程。 第一验证电压被施加到存储器单元以检测存储器单元的编程结果。 根据存储单元的编程结果调整施加在存储单元上的编程电压。 还提供闪存。

    FLASH MEMORY AND MEMORY CELL PROGRAMMING METHOD THEREOF
    8.
    发明申请
    FLASH MEMORY AND MEMORY CELL PROGRAMMING METHOD THEREOF 有权
    闪存存储器和存储器单元编程方法

    公开(公告)号：US20130044548A1

    公开(公告)日：2013-02-21

    申请号：US13211339

    申请日：2011-08-17

    申请人： Chun-Yuan Lo ,  Wein-Town Sun

    发明人： Chun-Yuan Lo ,  Wein-Town Sun

    IPC分类号： G11C16/10

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3459

    摘要： A flash memory and a memory cell programming method thereof are provided. The programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of the memory cell. A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell.

    摘要翻译： 提供闪存及其存储单元编程方法。 编程方法包括以下步骤。 将预设的编程电压施加到存储器单元以对存储器单元进行编程。 第一验证电压被施加到存储器单元以检测存储器单元的编程结果。 根据存储单元的编程结果调整施加在存储单元上的编程电压。

    MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
    存储器件及其制造方法

    公开(公告)号：US20110156102A1

    公开(公告)日：2011-06-30

    申请号：US13045153

    申请日：2011-03-10

    申请人： CHUN-YUAN LO ,  Cheng-Ming Yih ,  Wen-Pin Lu

    发明人： CHUN-YUAN LO ,  Cheng-Ming Yih ,  Wen-Pin Lu

    IPC分类号： H01L23/52 ,  H01L21/8239

    CPC分类号： H01L27/11519 ,  G11C5/005 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11565

    摘要： A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.

    摘要翻译： 提供包括多个存储单元，多个字线，虚拟字线，至少第一导电区域和至少第一插头的存储器阵列。 每个字线耦合到相应的存储单元。 虚拟字线与多个字线的最外侧字线直接相邻。 第一导电区域仅设置在虚拟字线和最外侧字线之间。 第一个插头位于虚拟字线和最外面的字线之间。