公开(公告)号：US20120273842A1

公开(公告)日：2012-11-01

申请号：US13549272

申请日：2012-07-13

申请人： Chun-Yuan Lo ,  Cheng-Ming Yih ,  Wen-Pin Lu

发明人： Chun-Yuan Lo ,  Cheng-Ming Yih ,  Wen-Pin Lu

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/11519 ,  G11C5/005 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11565

摘要： A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.

摘要翻译： 提供了包括多个存储单元，多个字线，虚拟字线和插头的存储器阵列。 每个字线耦合到相应的存储单元。 虚拟字线与多个字线的最外侧字线直接相邻。 插头位于虚拟字线和最外面的字线之间。

公开(公告)号：US20110156102A1

公开(公告)日：2011-06-30

申请号：US13045153

申请日：2011-03-10

申请人： CHUN-YUAN LO ,  Cheng-Ming Yih ,  Wen-Pin Lu

发明人： CHUN-YUAN LO ,  Cheng-Ming Yih ,  Wen-Pin Lu

IPC分类号： H01L23/52 ,  H01L21/8239

CPC分类号： H01L27/11519 ,  G11C5/005 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11565

摘要： A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.

摘要翻译： 提供包括多个存储单元，多个字线，虚拟字线，至少第一导电区域和至少第一插头的存储器阵列。 每个字线耦合到相应的存储单元。 虚拟字线与多个字线的最外侧字线直接相邻。 第一导电区域仅设置在虚拟字线和最外侧字线之间。 第一个插头位于虚拟字线和最外面的字线之间。

公开(公告)号：US20100323483A1

公开(公告)日：2010-12-23

申请号：US12851790

申请日：2010-08-06

申请人： Cheng-Ming Yih

发明人： Cheng-Ming Yih

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L29/7881 ,  H01L21/28247 ,  H01L21/28273 ,  H01L29/42324

摘要： A method of fabricating a semiconductor device is provided. First, a stacked structure is formed on a substrate. The stacked structure includes, from the substrate, a dielectric layer and a conductive gate in order. An ion implant process is performed to form doped regions in the substrate on the opposite sides of the stacked structure. Thereafter, source-side spacer is formed on a sidewall of the stacked structure. A thermal process is performed to activate the doped regions, thereby forming a source in the substrate under the sidewall of the stacked structure having the source-side spacer and a drain in the substrate on another side of the stacked structure.

摘要翻译： 提供一种制造半导体器件的方法。 首先，在基板上形成层叠结构。 叠层结构依次包括介质层和导电栅极。 执行离子注入工艺以在层叠结构的相对侧上的衬底中形成掺杂区域。 此后，在层叠结构的侧壁上形成源极间隔物。 执行热处理以激活掺杂区域，从而在层叠结构的侧壁的衬底内形成源，该层的结构具有源极侧隔离物和衬底中位于堆叠结构另一侧的漏极。

公开(公告)号：US07795665B2

公开(公告)日：2010-09-14

申请号：US11767192

申请日：2007-06-22

申请人： Cheng-Ming Yih

发明人： Cheng-Ming Yih

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28247 ,  H01L21/28273 ,  H01L29/42324

摘要： A flash memory comprising a substrate, a stacked structure over the substrate, a source, a drain and a source-side spacer is provided. The stacked structure includes a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The source and the drain are disposed in the substrate on the sides of the floating gate, respectively. The source-side spacer is disposed on a sidewall of the stacked structure near the source, thereby preventing the tunneling oxide layer and the inter-gate dielectric layer near the source from being re-oxidized, resulting in an increased thickness.

摘要翻译： 提供了一种闪存，其包括衬底，在衬底上的堆叠结构，源极，漏极和源极间隔物。 层叠结构包括隧道氧化物层，隧道氧化物层上的浮动栅极，浮置栅极上的栅极间介电层和栅极间电介质层上的控制栅极。 源极和漏极分别设置在浮动栅极的侧面上的衬底中。 源极间隔件设置在靠近源极的堆叠结构的侧壁上，从而防止源极附近的隧道氧化物层和栅极间电介质层被再次氧化，导致厚度增加。

公开(公告)号：US20090046516A1

公开(公告)日：2009-02-19

申请号：US11839255

申请日：2007-08-15

申请人： Chih-Hao Ho ,  Cheng-Ming Yih

发明人： Chih-Hao Ho ,  Cheng-Ming Yih

IPC分类号： G11C11/34

CPC分类号： G11C16/12

摘要： A data writing method for flash memories suitable for a flash memory using a switching unit to control a bit line thereof is disclosed. The data writing method for flash memories includes applying a square wave signal to a word line of the flash memory and applying a descent wave signal to the switching unit for the bit line of the flash memory to receive a fixed drain voltage.

摘要翻译： 公开了一种适用于使用切换单元来控制其位线的闪存的闪速存储器的数据写入方法。 用于闪速存储器的数据写入方法包括将方波信号施加到闪速存储器的字线，并将下降波信号施加到闪速存储器的位线的开关单元以接收固定的漏极电压。

公开(公告)号：US20060154441A1

公开(公告)日：2006-07-13

申请号：US11032045

申请日：2005-01-11

申请人： Cheng-Ming Yih ,  Huei-Huarng Chen ,  Hsuan-Ling Kao

发明人： Cheng-Ming Yih ,  Huei-Huarng Chen ,  Hsuan-Ling Kao

IPC分类号： H01L21/76

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.

摘要翻译： 提供一种在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法。 图案化的第一介电层形成在半导体衬底上用作第一硬掩模。 进行热氧化处理以在半导体衬底的暴露的部分上形成场氧化物。 然后去除图案化的第一介电层。 在场氧化物和半导体衬底上形成用作第二硬掩模的第二图案化电介质层。 执行各向同性蚀刻工艺以蚀刻场氧化物和半导体衬底的暴露部分。 图案化的第二介电层和下面的场氧化物被去除以在半导体衬底的表面上形成多个沟槽。 沿着半导体衬底中的沟槽的周围形成掩埋扩散层。

公开(公告)号：US08259499B2

公开(公告)日：2012-09-04

申请号：US12826280

申请日：2010-06-29

申请人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yi-Fan Chang ,  Su-chueh Lo ,  Cheng Ming Yih ,  Ta Kang Chu ,  Chu Ching Wu ,  Kuo Yu Liao ,  Ken Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C11/5635 ,  G11C16/0483 ,  G11C16/3418

摘要： Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

摘要翻译： 各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线 第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。 这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

公开(公告)号：US20110062507A1

公开(公告)日：2011-03-17

申请号：US12559781

申请日：2009-09-15

申请人： Tin-Wei Wu ,  Cheng-Ming Yih ,  Chih-Hsiang Yang

发明人： Tin-Wei Wu ,  Cheng-Ming Yih ,  Chih-Hsiang Yang

IPC分类号： H01L29/788

CPC分类号： H01L21/823468 ,  H01L21/823418 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66825

摘要： A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates.

摘要翻译： 提供半导体器件。 半导体器件包括存储器件，并且存储器件包括衬底，两个堆叠栅极，两个间隔物，绝缘层和介电层。 其间具有间隙的层叠栅极位于基板上。 在其间具有管或接缝的间隔件分别位于间隙中的每个堆叠栅极的侧壁处。 管或接缝填充有绝缘层。 电介质层位于衬底上并覆盖绝缘层和堆叠栅极。

公开(公告)号：US07846794B2

公开(公告)日：2010-12-07

申请号：US11943888

申请日：2007-11-21

申请人： Chu-Ching Wu ,  Cheng-Ming Yih

发明人： Chu-Ching Wu ,  Cheng-Ming Yih

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.

摘要翻译： 闪存单元包括具有主表面的硅衬底，位于主表面附近的硅衬底的一部分中的源极区域和靠近主表面的硅衬底的一部分中的漏极区域。 漏极区域与源极区域间隔开。 所述存储单元包括形成在所述主表面上的第一介电层，设置在所述第一介电层上方的浮置栅极，设置在所述浮置栅极上方的栅极间电介质层，设置在所述栅极间电介质层上方的控制栅极， 电介质层和设置在第二电介质层上的低k电介质间隔层。 第一电介质层覆盖源极和漏极之间的主表面的一部分。 第二电介质层围绕第一电介质层，控制栅极，栅极间电介质层和浮置栅极的外部部分。

公开(公告)号：US07663184B1

公开(公告)日：2010-02-16

申请号：US12183358

申请日：2008-07-31

申请人： Yao-Fu Chan ,  Ta-Kang Chu ,  Jung-Chuan Ting ,  Cheng-Ming Yih

发明人： Yao-Fu Chan ,  Ta-Kang Chu ,  Jung-Chuan Ting ,  Cheng-Ming Yih

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L29/7881

摘要： A memory and a method of fabricating the same are provided. The memory is disposed on a substrate in which a plurality of trenches is arranged in parallel. The memory includes a gate structure and a doped region. The gate structure is disposed between the trenches. The doped region is disposed at one side of the gate structure, in the substrate between the trenches and in the sidewalls and bottoms of the trenches. The top surface of the doped region in the substrate between the trenches is lower than the surface of the substrate under the gate structure by a distance, and the distance is greater than 300 Å.

摘要翻译： 提供了一种存储器及其制造方法。 存储器设置在其中多个沟槽平行布置的衬底上。 存储器包括栅极结构和掺杂区域。 栅极结构设置在沟槽之间。 掺杂区域设置在栅极结构的一侧，位于沟槽之间的衬底中以及沟槽的侧壁和底部中。 在沟槽之间的衬底中的掺杂区的顶表面比栅极结构下的衬底表面低一个距离，并且距离大于300。