公开(公告)号：US20090117701A1

公开(公告)日：2009-05-07

申请号：US11934053

申请日：2007-11-01

Applicant: Meng-Yi Wu ,  Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Chung-Min Shih ,  Yao-Chin Cheng ,  Tzyy-Ming Cheng

Inventor： Meng-Yi Wu ,  Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Chung-Min Shih ,  Yao-Chin Cheng ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/28247

Abstract: A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility.

Abstract translation: 制造MOS晶体管的方法包括在形成源极/漏极延伸区域之前执行热处理以修复损坏的衬底，因此减小了负偏压温度不稳定性（NBTI）。 由于在形成源极/漏极延伸区域之前进行热处理，因此不会影响用于形成源极/漏极延伸区域的热量预算和源极/漏极延伸部的结深度和结型材。 因此，所提供的制造MOS晶体管的方法能够减少短沟道效应并具有优异的工艺兼容性。

公开(公告)号：US20090239347A1

公开(公告)日：2009-09-24

申请号：US12469135

申请日：2009-05-20

Applicant: SHYH-FANN TING ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

Inventor： SHYH-FANN TING ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

IPC: H01L21/20 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract translation: 本发明提供一种形成金属氧化物半导体（MOS）器件的方法。 该方法至少包括通过选择性外延生长工艺形成硅锗层并通过选择性生长工艺在硅锗层上形成覆盖层的步骤。 因此，可以减轻离子注入引起的不良影响。

公开(公告)号：US08222113B2

公开(公告)日：2012-07-17

申请号：US12469135

申请日：2009-05-20

Applicant: Shyh-Fann Ting ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

Inventor： Shyh-Fann Ting ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method for forming a metal-oxide-semiconductor (MOS) device includes at least steps of forming a pair of trenches in a substrate at both sides of a gate structure, filling the trenches with a silicon germanium layer by a selective epitaxy growth process, forming a cap layer on the silicon germanium layer by a selective growth process, and forming a pair of source/drain regions by performing an ion implantation process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract translation: 形成金属氧化物半导体（MOS）器件的方法至少包括以下步骤：在栅极结构两侧的衬底中形成一对沟槽，通过选择性外延生长工艺用硅锗层填充沟槽， 通过选择性生长工艺在硅锗层上形成盖层，并通过进行离子注入工艺形成一对源/漏区。 因此，可以减轻离子注入引起的不良影响。

公开(公告)号：US20090224328A1

公开(公告)日：2009-09-10

申请号：US12041668

申请日：2008-03-04

Applicant: Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzer-Min Shen

Inventor： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzer-Min Shen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate defining an active area thereon, a shallow trench isolation on the substrate and directly surrounding the active area, a gate, a source and a drain on the active area and a hard mask on the border of the shallow trench isolation and the active area.

Abstract translation: 半导体器件包括限定其上的有源区的衬底，衬底上的浅沟槽隔离并且直接围绕有源区，有源区上的栅极，源极和漏极以及浅沟槽隔离边界上的硬掩模 和活动区域。

公开(公告)号：US20090186475A1

公开(公告)日：2009-07-23

申请号：US12017065

申请日：2008-01-21

Applicant: Shyh-Fann Ting ,  Cheng-Tung Huang ,  Shih-Chieh Hsu ,  Chih-Chiang Wu ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Yao-Chin Cheng ,  Chi-Sheng Tseng ,  Yu-Ming Lin ,  Shih-Jung Tu ,  Tzyy-Ming Cheng

Inventor： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Shih-Chieh Hsu ,  Chih-Chiang Wu ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Yao-Chin Cheng ,  Chi-Sheng Tseng ,  Yu-Ming Lin ,  Shih-Jung Tu ,  Tzyy-Ming Cheng

IPC: H01L21/3205

CPC classification number: H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

Abstract: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.

Abstract translation: 一种制造MOS晶体管的方法，其中使用三层光致抗蚀剂层来形成具有声音形状和小尺寸的图案化硬掩模层，并且使用图案化的硬掩模层来形成栅极。 此后，通过形成和限定盖层，通过在衬底中的蚀刻形成凹陷。 在凹槽中形成外延层之后去除图案化的硬掩模。 因此，可以避免导致接触桥的常规多晶块问题和STI氧化物损耗问题。

公开(公告)号：US20090166625A1

公开(公告)日：2009-07-02

申请号：US11966734

申请日：2007-12-28

Applicant: Shyh-Fann Ting ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

Inventor： Shyh-Fann Ting ,  Shih-Chieh Hsu ,  Cheng-Tung Huang ,  Chih-Chiang Wu ,  Wen-Han Hung ,  Meng-Yi Wu ,  Li-Shian Jeng ,  Chung-Min Shih ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng

IPC: H01L29/04 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract translation: 本发明提供一种形成金属氧化物半导体（MOS）器件的方法及其结构。 该方法至少包括通过第一选择性外延生长工艺形成硅锗层并通过第二选择性外延生长工艺在硅锗层上形成覆盖层的步骤。 因此，可以减轻离子注入引起的不良影响。

公开(公告)号：US20080237734A1

公开(公告)日：2008-10-02

申请号：US11693470

申请日：2007-03-29

Applicant: Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

Inventor： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Chung-Min Shih ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor.

Abstract translation: 提供了包括基板，第一导电型MOS晶体管，第二导电型MOS晶体管，缓冲层，第一应力层和第二应力层的互补金属氧化物半导体（CMOS）晶体管。 衬底在其中具有限定第一有源区和第二有源区的器件隔离结构。 第一导电型MOS晶体管和第二导电型MOS晶体管分别设置在基板的第一有源区域和第二有源区域中。 第一导电型MOS晶体管的第一氮化物间隔物的厚度大于第二导电型MOS晶体管的第二氮化物间隔物的厚度。 缓冲层设置在第一导电型MOS晶体管上。 第一应力层设置在缓冲层上。 第二应力层设置在第二导电型MOS晶体管上。

公开(公告)号：US20070099003A1

公开(公告)日：2007-05-03

申请号：US11389599

申请日：2006-03-24

Applicant: Ming-Kwei Lee ,  Chung-Min Shih ,  Tsung-Hsiang Shih

Inventor： Ming-Kwei Lee ,  Chung-Min Shih ,  Tsung-Hsiang Shih

IPC: B05D1/40 ,  B05D3/02 ,  B05D1/18 ,  B32B13/04 ,  B32B19/00

CPC classification number: B01J35/004 ,  B01J37/0215 ,  B01J37/031 ,  C03C17/256 ,  C03C2217/212 ,  C03C2218/113

Abstract: A titanate-containing material includes: a silicon-containing layer; and a crystalline layer of ammonium oxotrifluorotitanate formed on the silicon-containing layer. A method for making a titanate-containing material includes: immersing a silicon-containing substrate into an aqueous solution containing hexafluorotitanate radicals; and reacting the hexafluorotitanate radicals with water so as to form a crystalline layer of an oxotrifluorotitanate compound on the silicon-containing substrate.

Abstract translation: 含钛酸盐的材料包括：含硅层; 以及形成在含硅层上的氧化三氟钛酸铵的结晶层。 制备含钛酸盐材料的方法包括：将含硅基材浸入含有六氟钛酸酯基团的水溶液中; 并使六氟钛酸酯基团与水反应，以在含硅衬底上形成氧三氟钛酸盐化合物的结晶层。