公开(公告)号：US20080239629A1

公开(公告)日：2008-10-02

申请号：US11693365

申请日：2007-03-29

申请人： Barry J. Liles ,  Colin S. Whelan

发明人： Barry J. Liles ,  Colin S. Whelan

IPC分类号： H01L29/00 ,  H01G9/00 ,  H01L21/44

CPC分类号： H01L28/65 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  Y10S257/906 ,  H01L2924/00

摘要： A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.

摘要翻译： 一种用于减少与金属结构接触的电介质中的裂纹的方法和结构。 金属结构包括第一金属层; 设置在第一金属层上并与第一金属层接触的第二金属层，第二金属层比第一金属层更硬; 设置在第二金属层上并与第二金属层接触的第三金属层的第二金属层比第三金属层更硬。 包括另外的金属，其中介电层设置在金属结构和附加金属之间。

公开(公告)号：US06838325B2

公开(公告)日：2005-01-04

申请号：US10279358

申请日：2002-10-24

申请人： Colin S. Whelan ,  Elsa K. Tong

发明人： Colin S. Whelan ,  Elsa K. Tong

IPC分类号： H01L21/285 ,  H01L21/335 ,  H01L29/778 ,  H01L21/8252

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L29/7785

摘要： A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer. Next, a second wet chemical etch is brought into contact with structure etched by the first wet chemical etch. The second wet chemical etch selectively removes exposed portions of the ohmic contact layer while leaving substantially un-etched exposed portions of the third relatively wide band gap layer, the Schottky contact layer and the etch stop layer. The etch stop layer is removed. A metal layer is deposited over the mask and through gate aperture therein onto, and in Schottky contact with, the Schottky contact layer.

公开(公告)号：US06835969B1

公开(公告)日：2004-12-28

申请号：US10606820

申请日：2003-06-26

申请人： Philbert F. Marsh ,  Colin S. Whelan ,  William E. Hoke

发明人： Philbert F. Marsh ,  Colin S. Whelan ,  William E. Hoke

IPC分类号： H01L29/778

CPC分类号： H01L29/7784

摘要： A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an InyGa1-yAs lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an InxGa1-xAs upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the InxGa1-xAs upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.

摘要翻译： 具有砷化镓（GaAs）半导体衬底的晶体管结构; 一个格子匹配层; 设置在晶格匹配层上的铟铝砷化物（InAlAs）阻挡层; 设置在阻挡层上的InyGa1-yAs下通道层，其中y是下通道层中In含量的摩尔分数; 设置在下沟道层上的In x Ga 1-x As上沟道层，其中x是上沟道层中In含量的摩尔分数，其中x不同于y; 以及In x Ga 1-x As上沟道层上的InAlAs肖特基层。 下通道层的带隙大于上通道层的带隙。 下沟道层的体电子迁移率低于上沟道层的体电子迁移率。

公开(公告)号：US07609115B2

公开(公告)日：2009-10-27

申请号：US11851425

申请日：2007-09-07

申请人： Colin S. Whelan ,  John C. Tremblay

发明人： Colin S. Whelan ,  John C. Tremblay

IPC分类号： H03F3/191

CPC分类号： H03F1/565 ,  H03F3/1935 ,  H03F2200/222 ,  H03F2200/228 ,  H03F2200/249 ,  H03F2200/252 ,  H03F2200/451 ,  H03F2200/99 ,  H03H7/38

摘要： A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

摘要翻译： 一种具有输入匹配网络的电路; 耦合到所述输入匹配网络的输出的晶体管; 并且其中当所述输入匹配网络馈送具有相对较低功率电平的输入信号时，所述输入匹配网络具有第一输入阻抗，并且其中当所述输入匹配网络为所述输入匹配网络时，所述输入匹配网络具有与所述第一输入阻抗不同的输入阻抗 馈送具有相对较高功率电平的输入信号。

公开(公告)号：US06924218B2

公开(公告)日：2005-08-02

申请号：US10321310

申请日：2002-12-17

申请人： Philbert Francis Marsh ,  Colin S. Whelan

发明人： Philbert Francis Marsh ,  Colin S. Whelan

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/3213 ,  H01L21/335 ,  H01L21/44

CPC分类号： H01L21/32134 ,  H01L21/02057 ,  H01L21/02071 ,  H01L29/66462

摘要： A method for passivating a III-V material Schottky layer of a field effect transistor. The transistor has a gate electrode in Schottky contact with a gate electrode contact region of the Schottky layer. The gate electrode is adapted to control a flow of carriers between a source electrode of the transistor and a drain electrode of such tarnsistor. The transistor has exposed surface portions of the Schottky layer beween the source electrode and the drain electrode adjacent to the gate electrode contact region of the Schottky layer. The method includes removing organic contamination from the exposed surface portions of the Schottky layer using a oxygen plasma. The contamination removed surface portions of the Schottky layer are exposed to a solution of ammonium sulfide and NH4OH. After removal of the solution, the exposed regions are dried in a nitrogen enviroment. A layer of passivating material is deposited over the dried surface portions.

摘要翻译： 一种用于钝化场效应晶体管的III-V材料肖特基层的方法。 晶体管具有与肖特基层的栅电极接触区域肖特基接触的栅电极。 栅电极适于控制晶体管的源电极和这种电阻器的漏电极之间的载流子流。 晶体管具有暴露在肖特基层的与源极电极和漏电极相邻的肖特基层的表面部分，与肖特基层的栅电极接触区域相邻。 该方法包括使用氧等离子体从肖特基层的暴露表面部分去除有机污染物。 将去除的肖特基层表面部分的污染物暴露于硫化铵和NH 4 OH的溶液中。 除去溶液后，暴露的区域在氮环境中干燥。 一层钝化材料沉积在干燥的表面部分上。

公开(公告)号：US07863665B2

公开(公告)日：2011-01-04

申请号：US11693365

申请日：2007-03-29

申请人： Barry J. Liles ,  Colin S. Whelan

发明人： Barry J. Liles ,  Colin S. Whelan

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L28/65 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  Y10S257/906 ,  H01L2924/00

摘要： A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.

摘要翻译： 一种用于减少与金属结构接触的电介质中的裂纹的方法和结构。 金属结构包括第一金属层; 设置在第一金属层上并与第一金属层接触的第二金属层，第二金属层比第一金属层更硬; 设置在第二金属层上并与第二金属层接触的第三金属层的第二金属层比第三金属层更硬。 包括另外的金属，其中介电层设置在金属结构和附加金属之间。

公开(公告)号：US20090066439A1

公开(公告)日：2009-03-12

申请号：US11851425

申请日：2007-09-07

申请人： Colin S. Whelan ,  John C. Tremblay

发明人： Colin S. Whelan ,  John C. Tremblay

IPC分类号： H03H7/38

CPC分类号： H03F1/565 ,  H03F3/1935 ,  H03F2200/222 ,  H03F2200/228 ,  H03F2200/249 ,  H03F2200/252 ,  H03F2200/451 ,  H03F2200/99 ,  H03H7/38

摘要： A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

摘要翻译： 一种具有输入匹配网络的电路; 耦合到所述输入匹配网络的输出的晶体管; 并且其中当所述输入匹配网络馈送具有相对较低功率电平的输入信号时，所述输入匹配网络具有第一输入阻抗，并且其中当所述输入匹配网络为所述输入匹配网络时，所述输入匹配网络具有与所述第一输入阻抗不同的输入阻抗 馈送具有相对较高功率电平的输入信号。

公开(公告)号：US20090066411A1

公开(公告)日：2009-03-12

申请号：US11851418

申请日：2007-09-07

申请人： Colin S. Whelan ,  Raghu Mallavarpu ,  Matthew C. Tyhach

发明人： Colin S. Whelan ,  Raghu Mallavarpu ,  Matthew C. Tyhach

IPC分类号： H03F3/04

CPC分类号： H03F1/565 ,  H03F3/1935 ,  H03F2200/222 ,  H03F2200/249 ,  H03F2200/451 ,  H03H7/38

摘要： A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

摘要翻译： 一种具有输入匹配网络的电路; 耦合到所述输入匹配网络的输出的晶体管; 并且其中当所述输入匹配网络馈送具有相对较低功率电平的输入信号时，所述输入匹配网络具有第一输入阻抗，并且其中当所述输入匹配网络为所述输入匹配网络时，所述输入匹配网络具有与所述第一输入阻抗不同的输入阻抗 馈送具有相对较高功率电平的输入信号。

公开(公告)号：US07528649B2

公开(公告)日：2009-05-05

申请号：US11851418

申请日：2007-09-07

申请人： Colin S. Whelan ,  Raghu Mallavarpu ,  Matthew C. Tyhach

发明人： Colin S. Whelan ,  Raghu Mallavarpu ,  Matthew C. Tyhach

IPC分类号： G01R19/00

CPC分类号： H03F1/565 ,  H03F3/1935 ,  H03F2200/222 ,  H03F2200/249 ,  H03F2200/451 ,  H03H7/38

摘要： A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

摘要翻译： 一种具有输入匹配网络的电路; 耦合到所述输入匹配网络的输出的晶体管; 并且其中当所述输入匹配网络馈送具有相对较低功率电平的输入信号时，所述输入匹配网络具有第一输入阻抗，并且其中当所述输入匹配网络为所述输入匹配网络时，所述输入匹配网络具有与所述第一输入阻抗不同的输入阻抗 馈送具有相对较高功率电平的输入信号。