公开(公告)号：US06838325B2

公开(公告)日：2005-01-04

申请号：US10279358

申请日：2002-10-24

申请人： Colin S. Whelan ,  Elsa K. Tong

发明人： Colin S. Whelan ,  Elsa K. Tong

IPC分类号： H01L21/285 ,  H01L21/335 ,  H01L29/778 ,  H01L21/8252

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L29/7785

摘要： A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer. Next, a second wet chemical etch is brought into contact with structure etched by the first wet chemical etch. The second wet chemical etch selectively removes exposed portions of the ohmic contact layer while leaving substantially un-etched exposed portions of the third relatively wide band gap layer, the Schottky contact layer and the etch stop layer. The etch stop layer is removed. A metal layer is deposited over the mask and through gate aperture therein onto, and in Schottky contact with, the Schottky contact layer.

公开(公告)号：US07498223B2

公开(公告)日：2009-03-03

申请号：US11693762

申请日：2007-03-30

申请人： Kiuchul Hwang ,  Elsa K. Tong

发明人： Kiuchul Hwang ,  Elsa K. Tong

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/311

CPC分类号： H01L29/812 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316

摘要： A field effect transistor device and method, such device having source and drain electrodes in ohmic contact a semiconductor. A gate electrode-field plate structure is disposed between the source and drain electrodes. The gate electrode-field plate structure comprises: a dielectric; a first metal in Schottky contact the semiconductor; and a second metal. The second metal has: a first portion disposed over and electrically connected to a portion of the first metal; and a second portion, separated from a second portion of the first metal by a portion of the dielectric and extending beyond an edge of the first metal to an edge of the second metal. The edge of the first metal is further from the drain electrode than the edge of the second metal to provide a field-plate for the field effect transistor.

摘要翻译： 场效应晶体管器件和方法，这种器件具有与半导体欧姆接触的源极和漏极。 栅电极场结构设置在源极和漏极之间。 栅极电极 - 场板结构包括：电介质; 与半导体肖特基接触的第一金属; 和第二金属。 第二金属具有：设置在第一金属的一部分上并电连接的第一部分; 以及第二部分，其通过所述电介质的一部分与所述第一金属的第二部分分离并延伸超过所述第一金属的边缘到所述第二金属的边缘。 第一金属的边缘比漏极电极比第二金属的边缘更远，以提供场效应晶体管的场板。

公开(公告)号：US4794093A

公开(公告)日：1988-12-27

申请号：US44685

申请日：1987-05-01

申请人： Elsa K. Tong ,  Thomas E. Kazior

发明人： Elsa K. Tong ,  Thomas E. Kazior

IPC分类号： H01L21/308 ,  H01L21/74 ,  H01L23/367 ,  H01L23/48 ,  H01L19/00

CPC分类号： H01L21/743 ,  H01L21/308 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/10329 ,  Y10S148/026 ,  Y10S148/05 ,  Y10S148/105 ,  Y10S148/135

摘要： A technique for etching tub structures and vias on the backside of a wafer comprised of gallium arsenide and for providing a planar surface on said backside of the gallium arsenide wafer is described. The tubs are formed by providing a layer of resist over the backside of the gallium arsenide substrate, and this layer is patterned to provide selected areas covering regions where tub structures and vias will be provided. In the selectively exposed regions, palladium and gold are sequentially deposited. The resist pattern is then stripped, and a second resist layer pattern is deposited masking portions of the continuous conductive layer and areas where vias are to be provided. The tub structures are then provided by suitably etching the tub to undercut portions of the resist and the palladium layer. A second continuous conductive coating is then provided in the tub structure to provide a plating layer for subsequent plating of a gold film over the palladium. Preferably, the gold is plated to completely or substantially completely fill the tub. The vias are then provided on the backside of the wafer by masking the first continuous conductive coating and the tub regions and etching the unexposed regions of the substrate to provide the via holes. The via holes are then plated with a continuous conductive layer of palladium and then gold to substantially fill the via.

摘要翻译： 描述了在由砷化镓构成的晶片的背面上蚀刻槽结构和通孔并在砷化镓晶片的所述背面上提供平坦表面的技术。 通过在砷化镓衬底的背面上提供一层抗蚀剂来形成桶体，并且对该层进行图案化，以提供覆盖其中将提供桶结构和通孔的区域的选定区域。 在选择性暴露的区域中，依次沉积钯和金。 然后剥离抗蚀剂图案，并且沉积第二抗蚀剂层图案，掩蔽连续导电层的掩模部分和要设置通孔的区域。 然后通过适当地蚀刻桶以将抗蚀剂和钯层的部分倒下来提供浴缸结构。 然后在桶结构中提供第二连续导电涂层以提供用于随后在钯上镀覆金膜的镀层。 优选地，金被镀以完全或基本上完全填充桶。 然后通过掩蔽第一连续导电涂层和桶区并且蚀刻基板的未曝光区域以提供通孔，将通孔设置在晶片的背面。 然后将通孔用镀钯的连续导电层然后镀金，以基本上填充通孔。

公开(公告)号：US6087207A

公开(公告)日：2000-07-11

申请号：US163124

申请日：1998-09-29

申请人： Elsa K. Tong

发明人： Elsa K. Tong

IPC分类号： H01L29/812 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L29/7783

摘要： A method for forming a gate of a field effect transistor wherein a structure is provided having: a gallium arsenide substrate; an indium gallium arsenide channel layer over the substrate; a doped aluminum gallium arsenide barrier layer over the channel layer; a gallium arsenide protective layer disposed on the donor layer; an indium gallium phosphide etch stop layer disposed over the protective layer; and a gallium arsenide source and drain contact layer disposed over the etch stop layer. A mask is provided over the surface of the structure to expose a surface portion of the contact layer. The exposed surface portion of the contact layer is subjected to a first etch and etching through the contact layer to expose an underlying surface portion of the etch stop layer. The first etch etches the contact layer at a substantially greater etch rate than the etch rate of such etch to the etch stop layer. The exposed surface portion of the etch stop layer is then subjected to a second etch and etching through the etch stop layer to expose an underlying surface portion of the protective layer. The second etch etches the etch stop layer at a substantially greater etch rate than the etch rate of such second etch to the protective layer. A gate metal is deposited over the mask and through etched portions of the etch stop layer onto, and in Schottky contact with the exposed portion of the protective layer. The method allows the formation of a gate recess by selective wet etching thereby eliminating surface damage associated with a dry etch and ungated recess. Because of the wet etching selectivity measurement of the channel current is eliminated to determine the etching end point.

摘要翻译： 一种用于形成场效应晶体管的栅极的方法，其中提供了具有砷化镓衬底的结构; 在衬底上的砷化铟镓通道层; 沟道层上的掺杂的砷化铝镓屏障层; 设置在供体层上的砷化镓保护层; 设置在所述保护层上的铟镓磷化物蚀刻停止层; 以及设置在蚀刻停止层上方的砷化镓源极和漏极接触层。 在结构的表面上设置掩模以暴露接触层的表面部分。 对接触层的暴露的表面部分进行第一蚀刻和蚀刻，通过接触层暴露蚀刻停止层的下面的表面部分。 第一蚀刻以比蚀刻停止层的这种蚀刻的蚀刻速率大得多的蚀刻速率蚀刻接触层。 然后对蚀刻停止层的暴露的表面部分进行第二蚀刻和蚀刻，通过蚀刻停止层暴露保护层的下面的表面部分。 蚀刻停止层的蚀刻蚀刻速率比对第二蚀刻对保护层的蚀刻速率要大得多。 栅极金属沉积在掩模上，并通过蚀刻停止层的蚀刻部分沉积到保护层的暴露部分上并以肖特基接触。 该方法允许通过选择性湿蚀刻形成栅极凹槽，从而消除与干蚀刻和非栅极凹槽相关联的表面损伤。 由于湿蚀刻选择性测量通道电流被消除以确定蚀刻终点。

公开(公告)号：US4970578A

公开(公告)日：1990-11-13

申请号：US250193

申请日：1988-09-28

申请人： Elsa K. Tong ,  Thomas E. Kazior

发明人： Elsa K. Tong ,  Thomas E. Kazior

IPC分类号： H01L21/308 ,  H01L21/74 ,  H01L23/367 ,  H01L23/48

CPC分类号： H01L21/308 ,  H01L21/743 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/10329

摘要： A technique for etching tub structures and vias on the backside of a wafer comprised of gallium arsenide and for providing a planar surface on said backside of the gallium arsenide wafer is described. The tubs are formed by providing a layer of resist over the backside of the gallium arsenide substrate, and this layer is patterned to provide selected areas covering regions where tub structures and vias will be provided. In the selectively exposed regions, palladium and gold are sequentially deposited. The resist pattern is then stripped, and a second resist layer pattern is deposited masking portions of the continuous conductive layer and areas where vias are to be provided. The tub structures are then provided by suitably etching the tub to undercut portions of the resist and the palladium layer. A second continuous conductive coating is then provided in the tub structure to provide a plating layer for subsequent plating of a gold film over the palladium. Preferably, the gold is plated to completely or substantially completely fill the tub. The vias are then provided on the backside of the wafer by masking the first continuous conductive coating and the tub regions and etching the unexposed regions of the substrate to provide the via holes. The via holes are then plated with a continuous conductive layer of palladium and then gold to substantially fill the via.

摘要翻译： 描述了在由砷化镓构成的晶片的背面上蚀刻槽结构和通孔并在砷化镓晶片的所述背面上提供平坦表面的技术。 通过在砷化镓衬底的背面上提供一层抗蚀剂来形成桶体，并且对该层进行图案化，以提供覆盖其中将提供桶结构和通孔的区域的选定区域。 在选择性暴露的区域中，依次沉积钯和金。 然后剥离抗蚀剂图案，并且沉积第二抗蚀剂层图案，掩蔽连续导电层的掩模部分和要设置通孔的区域。 然后通过适当地蚀刻桶以将抗蚀剂和钯层的部分倒下来提供浴缸结构。 然后在桶结构中提供第二连续导电涂层以提供用于随后在钯上镀覆金膜的镀层。 优选地，金被镀以完全或基本上完全填充桶。 然后通过掩蔽第一连续导电涂层和桶区并且蚀刻基板的未曝光区域以提供通孔，将通孔设置在晶片的背面。 然后将通孔用镀钯的连续导电层然后镀金，以基本上填充通孔。