公开(公告)号：US07563677B2

公开(公告)日：2009-07-21

申请号：US11531239

申请日：2006-09-12

Applicant: Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

Inventor： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

IPC: H01L21/336

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

Abstract: A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

Abstract translation: 凹陷栅极电极结构包括第一凹部和与形成在基板中的第一凹部连通的第二凹部。 第二凹部比第一凹部大。 栅极电介质层形成在基板的顶表面上和第一凹槽和第二凹槽的内表面上。 第一多晶硅层填充第一凹槽并以第一杂质密度掺杂杂质。 第二多晶硅层填充第二凹槽，并以第二杂质密度掺杂杂质。 在第二多晶硅层内限定空隙。 在栅极电介质和第一多晶硅层上形成第三多晶硅层，并以第三杂质密度掺杂杂质。 由于第二多晶硅层中的杂质，可以基本上防止第二凹陷内的空隙的迁移。

公开(公告)号：US20110275197A1

公开(公告)日：2011-11-10

申请号：US13100680

申请日：2011-05-04

Applicant: Hong-bum PARK ,  Dae-Han Yoo ,  Eun-Young Lee ,  Yongwoo Hyung ,  Youngsub You ,  Jinkwon Bok

Inventor： Hong-bum PARK ,  Dae-Han Yoo ,  Eun-Young Lee ,  Yongwoo Hyung ,  Youngsub You ,  Jinkwon Bok

IPC: H01L21/20

CPC classification number: H01L27/11578 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L27/10852 ,  H01L27/11582 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of forming a semiconductor memory device, a semiconductor memory device, and a memory system, the method including forming a thin film structure on a semiconductor substrate such that the thin film structure includes a plurality of thin films; patterning the thin film structure to form a through region in the thin film structure; forming a first silicon film using a first precursor such that the first silicon film covers the through region; and forming a second silicon film on the first silicon film using a second precursor, wherein the first precursor is different from the second precursor.

Abstract translation: 一种形成半导体存储器件，半导体存储器件和存储器系统的方法，所述方法包括在半导体衬底上形成薄膜结构，使得薄膜结构包括多个薄膜; 图案化薄膜结构以在薄膜结构中形成贯穿区域; 使用第一前体形成第一硅膜，使得第一硅膜覆盖通孔区域; 以及使用第二前体在所述第一硅膜上形成第二硅膜，其中所述第一前体与所述第二前体不同。

公开(公告)号：US20070059889A1

公开(公告)日：2007-03-15

申请号：US11531239

申请日：2006-09-12

Applicant: Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung KIM ,  Jung-Hwan OH ,  Young-Sub You

Inventor： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung KIM ,  Jung-Hwan OH ,  Young-Sub You

IPC: H01L21/336

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

Abstract: A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to the presence of impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

Abstract translation: 凹陷栅极电极结构包括第一凹部和与形成在基板中的第一凹部连通的第二凹部。 第二凹部比第一凹部大。 栅极电介质层形成在基板的顶表面上和第一凹槽和第二凹槽的内表面上。 第一多晶硅层填充第一凹槽并以第一杂质密度掺杂杂质。 第二多晶硅层填充第二凹槽，并以第二杂质密度掺杂杂质。 在第二多晶硅层内限定空隙。 在栅极电介质和第一多晶硅层上形成第三多晶硅层，并以第三杂质密度掺杂杂质。 由于在第二多晶硅层中存在杂质，可以基本上防止第二凹陷内的空隙的迁移。

公开(公告)号：US20080305572A1

公开(公告)日：2008-12-11

申请号：US12132542

申请日：2008-06-03

Applicant: Young-Sub YOU ,  Dae-Han YOO ,  Yong-Woo HYUNG ,  Jae-Jong HAN ,  Bi-O KIM ,  Gil-Hwan SON

Inventor： Young-Sub YOU ,  Dae-Han YOO ,  Yong-Woo HYUNG ,  Jae-Jong HAN ,  Bi-O KIM ,  Gil-Hwan SON

IPC: H01L31/18 ,  H01L21/02

CPC classification number: H01L27/14609 ,  H01L27/14687 ,  H01L28/40

Abstract: There are provided a method of fabricating an image device having a capacitor and an image device fabricated thereby. The method comprises preparing a substrate having a pixel region and a peripheral circuit region. A lower electrode containing silicon is formed on the substrate of the peripheral circuit region. A capacitor dielectric layer is formed by sequentially stacking a first dielectric layer and a second dielectric layer on the lower electrode, and the first dielectric layer and the second dielectric layer have a different dielectric constant from each other. In this case, one of the first and second dielectric layers is a dielectric layer grown from a material layer formed thereunder and has a lower dielectric constant than that of the other. An upper electrode is formed on the capacitor dielectric layer.

Abstract translation: 提供了一种制造具有电容器和由其制造的图像器件的图像器件的方法。 该方法包括制备具有像素区域和外围电路区域的衬底。 在外围电路区域的基板上形成含有硅的下部电极。 通过在下电极上依次层叠第一电介质层和第二电介质层而形成电容电介质层，第一电介质层和第二电介质层的介电常数彼此不同。 在这种情况下，第一和第二电介质层中的一个是从其下形成的材料层生长的介电层，并且具有比另一个更低的介电常数。 在电容器电介质层上形成上电极。