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    Recessed gate electrode and method of forming the same and semiconductor device having the recessed gate electrode and method of manufacturing the same
    1.
    发明授权
    Recessed gate electrode and method of forming the same and semiconductor device having the recessed gate electrode and method of manufacturing the same 有权
    嵌入式栅电极及其形成方法以及具有凹陷栅电极的半导体器件及其制造方法

    公开(公告)号：US07563677B2

    公开(公告)日：2009-07-21

    申请号：US11531239

    申请日：2006-09-12

    申请人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

    发明人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

    摘要： A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

    摘要翻译： 凹陷栅极电极结构包括第一凹部和与形成在基板中的第一凹部连通的第二凹部。 第二凹部比第一凹部大。 栅极电介质层形成在基板的顶表面上和第一凹槽和第二凹槽的内表面上。 第一多晶硅层填充第一凹槽并以第一杂质密度掺杂杂质。 第二多晶硅层填充第二凹槽，并以第二杂质密度掺杂杂质。 在第二多晶硅层内限定空隙。 在栅极电介质和第一多晶硅层上形成第三多晶硅层，并以第三杂质密度掺杂杂质。 由于第二多晶硅层中的杂质，可以基本上防止第二凹陷内的空隙的迁移。

    CMOS IMAGE SENSORS AND METHODS OF FABRICATING SAME
    3.
    发明申请
    CMOS IMAGE SENSORS AND METHODS OF FABRICATING SAME 审中-公开
    CMOS图像传感器及其制造方法

    公开(公告)号：US20080296644A1

    公开(公告)日：2008-12-04

    申请号：US12187103

    申请日：2008-08-06

    申请人： Young-Sub You ,  Jung-Hwan Oh ,  Yong-Woo Hyung ,  Hun-Hyoung Lim

    发明人： Young-Sub You ,  Jung-Hwan Oh ,  Yong-Woo Hyung ,  Hun-Hyoung Lim

    IPC分类号： H01L27/146 ,  H01L21/28

    CPC分类号： H01L27/14623 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689

    摘要： A CMOS image sensor includes an image transfer transistor therein. This image transfer transistor includes a semiconductor channel region of first conductivity type and an electrically conductive gate on the semiconductor channel region. A gate insulating region is also provided. The gate insulating region extends between the semiconductor channel region and the electrically conductive gate. The gate insulating region includes a nitridated insulating layer extending to an interface with the electrically conductive gate and a substantially nitrogen-free insulating layer extending to an interface with the semiconductor channel region. The nitridated insulating layer may be a silicon oxynitride (SiON) layer.

    摘要翻译： CMOS图像传感器包括其中的图像转移晶体管。 该图像传输晶体管包括半导体沟道区上的第一导电类型的半导体沟道区和导电栅。 还提供了栅极绝缘区域。 栅极绝缘区域在半导体沟道区域和导电栅极之间延伸。 栅极绝缘区域包括延伸到与导电栅极的界面的氮化绝缘层和延伸到与半导体沟道区域的界面的基本上无氮的绝缘层。 氮化绝缘层可以是氮氧化硅（SiON）层。

    Method for forming capacitor using etching stopper film in semiconductor memory
    4.
    发明申请
    Method for forming capacitor using etching stopper film in semiconductor memory 审中-公开
    在半导体存储器中使用蚀刻阻挡膜形成电容器的方法

    公开(公告)号：US20050153518A1

    公开(公告)日：2005-07-14

    申请号：US11012403

    申请日：2004-12-15

    申请人： Young-Sub You ,  Jung-Hwan Oh ,  Ki-Su Na ,  Seok-Woo Nam ,  Hun-Hyeoung Leam

    发明人： Young-Sub You ,  Jung-Hwan Oh ,  Ki-Su Na ,  Seok-Woo Nam ,  Hun-Hyeoung Leam

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/20

    CPC分类号： H01L28/91 ,  H01L27/10852

    摘要： A method for forming a capacitor comprises forming a supporting insulating film, an etching stopper film made of alumina series or hafnium oxide series, and a mold insulating film on a surface of a semiconductor substrate having a first structure including conductive plugs surrounded by a first insulating film, patterning the mold insulating film, the etching stopper film and the supporting insulating film to form openings that expose the conductive plugs, forming a storage node conductive film electrically connected to the conductive plugs on the surface of the semiconductor substrate having the openings formed therein and concurrently annealing the etching stopper film, separating the storage node conductive film to form a plurality of storage nodes, exposing at least a part of an outer surface of the storage node by selectively etching remaining mold insulating film, which is exposed by the separated storage node conductive film, until the etching stopper film is exposed, and forming a plurality of plate nodes on the plurality of storage nodes with a dielectric film disposed therebetween.

    摘要翻译： 一种形成电容器的方法，包括形成支撑绝缘膜，由氧化铝系列或氧化铪系列制成的蚀刻阻挡膜，以及在具有第一结构的半导体衬底的表面上的模具绝缘膜，该第一结构包括由第一绝缘体 膜，图案化模具绝缘膜，蚀刻停止膜和支撑绝缘膜，以形成露出导电插塞的开口，形成与其上形成有开口的半导体衬底的表面上的导电插塞电连接的存储节点导电膜 并且同时退火所述蚀刻停止膜，分离所述存储节点导电膜以形成多个存储节点，通过选择性地蚀刻剩余的模制绝缘膜，暴露所述存储节点的外表面的至少一部分， 节点导电膜，直到蚀刻停止膜暴露，并形成 g多个存储节点上的多个平板节点，其间设置介电膜。

    Method of oxidizing a silicon substrate and method of forming an oxide layer using the same
    5.
    发明授权
    Method of oxidizing a silicon substrate and method of forming an oxide layer using the same 有权
    氧化硅衬底的方法和使用其形成氧化物层的方法

    公开(公告)号：US07119029B2

    公开(公告)日：2006-10-10

    申请号：US10839501

    申请日：2004-05-05

    申请人： Won-Sik Shin ,  Ki-Hyun Hwang ,  Jung-Hwan Oh ,  Hyeon-Deok Lee ,  Seok-Woo Nam

    发明人： Won-Sik Shin ,  Ki-Hyun Hwang ,  Jung-Hwan Oh ,  Hyeon-Deok Lee ,  Seok-Woo Nam

    IPC分类号： H01L23/48

    CPC分类号： H01L21/02238 ,  C23C8/12 ,  C23C8/28 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/3144

    摘要： In a method of forming an oxide layer, ozone is generated by reacting an oxygen gas having a first flow rate with a nitrogen gas having a second flow rate of more than about 1% of the first flow rate. A reactant including the ozone and nitrogen is provided onto a silicon substrate. A surface of the silicon substrate is oxidized via the reaction of the reactant with silicon in the silicon substrate. The flow rate of the nitrogen gas is increased while ozone serving as an oxidant is formed by reacting the nitrogen gas with the oxygen gas. Thus, the oxide layer or a metal oxide layer including nitrogen may be rapidly formed on the substrate.

    摘要翻译： 在形成氧化物层的方法中，通过使具有第一流量的氧气与具有大于第一流量的约1％的第二流量的氮气反应来生成臭氧。 将包含臭氧和氮的反应物提供到硅衬底上。 硅衬底的表面通过反应物与硅衬底中的硅的反应被氧化。 通过使氮气与氧气反应而形成臭氧作为氧化剂，氮气的流量增加。 因此，可以在衬底上快速形成包含氮的氧化物层或金属氧化物层。

    Method of manufacturing a hemisperical grain silicon layer and method of manufacturing a semiconductor device using the same
    6.
    发明申请
    Method of manufacturing a hemisperical grain silicon layer and method of manufacturing a semiconductor device using the same 审中-公开
    制造半晶粒硅层的方法及使用其制造半导体器件的方法

    公开(公告)号：US20060160337A1

    公开(公告)日：2006-07-20

    申请号：US11323999

    申请日：2005-12-29

    申请人： Young-Jin Kim ,  Hyeon-Deok Lee ,  Seok-Woo Nam ,  Yong-Jae Lee ,  Hyun-Seok Lim ,  Wan-Goo Hwang ,  Jin-Il Lee ,  Jung-Hwan Oh

    发明人： Young-Jin Kim ,  Hyeon-Deok Lee ,  Seok-Woo Nam ,  Yong-Jae Lee ,  Hyun-Seok Lim ,  Wan-Goo Hwang ,  Jin-Il Lee ,  Jung-Hwan Oh

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L28/84 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

    摘要： In a method of manufacturing a capacitor including a hemispherical grain (HSG) silicon layer, after forming a storage electrode electrically coupled to a contact region of a substrate, the HSG silicon layer is formed on the storage electrode by providing a first gas including silicon and a second gas onto a surface of the storage electrode with a volume ratio of about 1.0:0.1 to about 1.0:5.0. A dielectric layer and a plate electrode are sequentially formed on the HSG silicon layer. A grain size of the HSG silicon layer may be easily adjusted and abnormal growths of the HSG at a lower portion of the storage electrode may be suppressed. Therefore, the HSG silicon layer may be uniformly formed on the storage electrode, and a structural stability of the storage electrode may be improved to prevent electrical defects of the capacitor.

    摘要翻译： 在制造包括半球形晶粒（HSG）硅层的电容器的方法中，在形成与基板的接触区域电耦合的存储电极之后，通过提供包括硅的第一气体和存储电极形成HSG硅层， 第二气体以约1.0:0.1至约1.0:5.0的体积比存储在存储电极的表面上。 在HSG硅层上依次形成电介质层和平板电极。 可以容易地调节HSG硅层的晶粒尺寸，并且可以抑制存储电极下部的HSG的异常生长。 因此，HSG硅层可以均匀地形成在存储电极上，并且可以改善存储电极的结构稳定性，以防止电容器的电缺陷。

    One-cylinder stack capacitor and method for fabricating the same
    9.
    发明授权
    One-cylinder stack capacitor and method for fabricating the same 有权
    单缸电容器及其制造方法

    公开(公告)号：US06911364B2

    公开(公告)日：2005-06-28

    申请号：US10687838

    申请日：2003-10-20

    申请人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

    发明人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/91 ,  H01L27/10855

    摘要： An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

    摘要翻译： 在层间绝缘层的表面上方和在从层间绝缘层的表面的深度延伸的导电插塞的表面之上形成蚀刻停止层。 在蚀刻停止层上沉积下模层，并且通过在形成下模层期间向下模层添加掺杂剂并且通过对下模层进行退火来调节下模层的湿蚀刻速率。 然后将上模层沉积在下模层的表面上，使得上模层的湿蚀刻速率小于下模层的经调整的湿蚀刻速率。 然后对上模层，下模层和蚀刻停止层进行干蚀刻以在其中形成露出接触塞表面的至少一部分的开口。 然后进行上模层和下模层的湿式蚀刻，以便增加下模层上开口的尺寸，从而暴露出邻近导电塞表面的蚀刻停止层的表面部分 。 然后将导电材料沉积在上模具层和下模层中的开口的表面上，以限定电容器电极。