公开(公告)号：US20120009781A1

公开(公告)日：2012-01-12

申请号：US13240109

申请日：2011-09-22

Applicant: Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

Inventor： Kyung-In Choi ,  Hyeon-Deok Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11546 ,  H01L27/11548

Abstract: In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.

Abstract translation: 在制造金属布线结构的方法中，在基板上形成第一金属布线和第一阻挡层，并且对第一阻挡层进行氮化。 绝缘中间层形成在基板上，以便延伸越过第一金属布线和第一阻挡层。 去除部分绝缘中间层以形成露出第一金属布线和第一阻挡层的一部分的至少一部分的孔。 在第一阻挡层的暴露部分上进行氮化等离子体处理。 沿着孔的底部和侧面形成第二阻挡层。 在第二阻挡层上形成插塞以填充孔。

公开(公告)号：US07524724B2

公开(公告)日：2009-04-28

申请号：US11173771

申请日：2005-06-30

Applicant: Rak-Hwan Kim ,  Hyun-Seok Lim ,  Young-Joo Cho ,  In-Sun Park ,  Hyeon-Deok Lee ,  Hyun-Suk Lee

Inventor： Rak-Hwan Kim ,  Hyun-Seok Lim ,  Young-Joo Cho ,  In-Sun Park ,  Hyeon-Deok Lee ,  Hyun-Suk Lee

IPC: H01L21/20

CPC classification number: C23C16/45529 ,  C23C16/34 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91

Abstract: A method of fabricating a storage capacitor includes depositing a first titanium nitride layer on a dielectric layer using a chemical vapor deposition technique or an atomic layer deposition technique performed at a first temperature with reactant gases of titanium chloride (TiCl4) gas and ammonia (NH3) gas at a predetermined flow ratio and depositing a second titanium nitride layer on the first titanium nitride layer using a chemical vapor deposition process performed at a second temperature that is greater than the first temperature with reactant gases of titanium chloride (TiCl4) gas and ammonia (NH3) gas.

Abstract translation: 一种制造存储电容器的方法包括使用化学气相沉积技术或在第一温度下用氯化钛（TiCl 4）气体和氨（NH 3））的反应气体进行的原子层沉积技术在电介质层上沉积第一氮化钛层， 气体以预定的流量比并且在第二氮化钛层上沉积第二氮化钛层，所述化学气相沉积工艺是在第二温度下用氯化钛（TiCl 4）气体和氨的反应气体 NH3）气体。

公开(公告)号：US07504725B2

公开(公告)日：2009-03-17

申请号：US10915871

申请日：2004-08-09

Applicant: Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

Inventor： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

IPC: H01L23/52

CPC classification number: H01L23/485 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76876 ,  H01L27/10885 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.

Abstract translation: 一种半导体存储器件和半导体存储器件的制造方法，其中位线可以具有低电阻而不增加位线的厚度。 在半导体存储器件中，在具有导电区域的半导体衬底上形成具有暴露导电区域的接触孔的绝缘层。 沿着绝缘层的表面和接触孔的表面形成阻挡金属层。 在阻挡金属层与钨层之间形成晶粒控制层。 在晶粒控制层上形成钨层。 钨层的晶粒尺寸由晶粒控制层增加。

公开(公告)号：US07125774B2

公开(公告)日：2006-10-24

申请号：US10937532

申请日：2004-09-08

Applicant: Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

Inventor： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/3205

CPC classification number: H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

Abstract: A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

Abstract translation: 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

公开(公告)号：US07119029B2

公开(公告)日：2006-10-10

申请号：US10839501

申请日：2004-05-05

Applicant: Won-Sik Shin ,  Ki-Hyun Hwang ,  Jung-Hwan Oh ,  Hyeon-Deok Lee ,  Seok-Woo Nam

Inventor： Won-Sik Shin ,  Ki-Hyun Hwang ,  Jung-Hwan Oh ,  Hyeon-Deok Lee ,  Seok-Woo Nam

IPC: H01L23/48

CPC classification number: H01L21/02238 ,  C23C8/12 ,  C23C8/28 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/3144

Abstract: In a method of forming an oxide layer, ozone is generated by reacting an oxygen gas having a first flow rate with a nitrogen gas having a second flow rate of more than about 1% of the first flow rate. A reactant including the ozone and nitrogen is provided onto a silicon substrate. A surface of the silicon substrate is oxidized via the reaction of the reactant with silicon in the silicon substrate. The flow rate of the nitrogen gas is increased while ozone serving as an oxidant is formed by reacting the nitrogen gas with the oxygen gas. Thus, the oxide layer or a metal oxide layer including nitrogen may be rapidly formed on the substrate.

Abstract translation: 在形成氧化物层的方法中，通过使具有第一流量的氧气与具有大于第一流量的约1％的第二流量的氮气反应来生成臭氧。 将包含臭氧和氮的反应物提供到硅衬底上。 硅衬底的表面通过反应物与硅衬底中的硅的反应被氧化。 通过使氮气与氧气反应而形成臭氧作为氧化剂，氮气的流量增加。 因此，可以在衬底上快速形成包含氮的氧化物层或金属氧化物层。

公开(公告)号：US20060145269A1

公开(公告)日：2006-07-06

申请号：US11365063

申请日：2006-02-28

Applicant: Jung-Wook Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

Inventor： Jung-Wook Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

IPC: H01L29/94 ,  H01L23/48

CPC classification number: H01L23/485 ,  H01L21/76841 ,  H01L21/7685 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.

公开(公告)号：US20050054163A1

公开(公告)日：2005-03-10

申请号：US10937532

申请日：2004-09-08

Applicant: Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

Inventor： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

Abstract: A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

Abstract translation: 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

公开(公告)号：US20050042829A1

公开(公告)日：2005-02-24

申请号：US10915871

申请日：2004-08-09

Applicant: Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

Inventor： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485

CPC classification number: H01L23/485 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76876 ,  H01L27/10885 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.

Abstract translation: 一种半导体存储器件和半导体存储器件的制造方法，其中位线可以具有低电阻而不增加位线的厚度。 在半导体存储器件中，在具有导电区域的半导体衬底上形成具有暴露导电区域的接触孔的绝缘层。 沿着绝缘层的表面和接触孔的表面形成阻挡金属层。 在阻挡金属层与钨层之间形成晶粒控制层。 在晶粒控制层上形成钨层。 钨层的晶粒尺寸由晶粒控制层增加。

公开(公告)号：US07410869B2

公开(公告)日：2008-08-12

申请号：US11480380

申请日：2006-07-05

Applicant: Hun-Hyeoung Leam ,  Hyeon-Deok Lee ,  Young-Sub You ,  Won-Jun Jang ,  Woong Lee ,  Jung-Hyun Park ,  Sang-Kyoung Lee ,  Jung-Geun Jee ,  Sang-Hoon Lee

Inventor： Hun-Hyeoung Leam ,  Hyeon-Deok Lee ,  Young-Sub You ,  Won-Jun Jang ,  Woong Lee ,  Jung-Hyun Park ,  Sang-Kyoung Lee ,  Jung-Geun Jee ,  Sang-Hoon Lee

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L21/32115 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.

Abstract translation: 在制造诸如闪速存储器件的半导体器件的方法中，形成具有开口的绝缘图案以部分地暴露衬底的表面。 第一硅层形成在基板的露出表面部分和绝缘图案上。 第一硅层具有覆盖衬底的先前暴露部分的开口接缝。 在足以诱导硅迁移的温度下进行在基板上的热处理，以便通过硅迁移使开放的接缝闭合。 然后在第一硅层上形成第二硅层。 因此，可以提高从第一和第二硅层获得的浮栅的表面轮廓。

公开(公告)号：US07311109B2

公开(公告)日：2007-12-25

申请号：US10606512

申请日：2003-06-26

Applicant: Jung-wook Kim ,  Hyeon-Deok Lee ,  Jin-Gi Hong ,  Ji-Soon Park ,  Eung-Joon Lee

Inventor： Jung-wook Kim ,  Hyeon-Deok Lee ,  Jin-Gi Hong ,  Ji-Soon Park ,  Eung-Joon Lee

IPC: B08B9/00 ,  H01L21/00

CPC classification number: C23C16/4405 ,  C23C16/0245 ,  H01L21/02063 ,  H01L21/76814 ,  Y10S438/905

Abstract: A method for cleaning a processing chamber and manufacturing a semiconductor device by removing impurities from a substrate in the processing chamber with a plasma of a first gas including hydrogen gas. After the substrate is removed from the processing chamber, the processing chamber is etched with the plasma of a non-hydrogenous second gas. Thus, the etching selectivity can be improved and the particles are prevented from depositing and/or forming on the substrate.

Abstract translation: 一种清洗处理室的方法，并且利用包含氢气的第一气体的等离子体从处理室中的基板上除去杂质来制造半导体器件。 在从处理室移除基板之后，用非氢气的第二气体的等离子体蚀刻处理室。 因此，可以提高蚀刻选择性，并且防止颗粒在衬底上沉积和/或形成。