公开(公告)号：US07563677B2

公开(公告)日：2009-07-21

申请号：US11531239

申请日：2006-09-12

申请人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

发明人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

摘要： A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

摘要翻译： 凹陷栅极电极结构包括第一凹部和与形成在基板中的第一凹部连通的第二凹部。 第二凹部比第一凹部大。 栅极电介质层形成在基板的顶表面上和第一凹槽和第二凹槽的内表面上。 第一多晶硅层填充第一凹槽并以第一杂质密度掺杂杂质。 第二多晶硅层填充第二凹槽，并以第二杂质密度掺杂杂质。 在第二多晶硅层内限定空隙。 在栅极电介质和第一多晶硅层上形成第三多晶硅层，并以第三杂质密度掺杂杂质。 由于第二多晶硅层中的杂质，可以基本上防止第二凹陷内的空隙的迁移。

公开(公告)号：US20070059889A1

公开(公告)日：2007-03-15

申请号：US11531239

申请日：2006-09-12

申请人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung KIM ,  Jung-Hwan OH ,  Young-Sub You

发明人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung KIM ,  Jung-Hwan OH ,  Young-Sub You

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

摘要： A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to the presence of impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

摘要翻译： 凹陷栅极电极结构包括第一凹部和与形成在基板中的第一凹部连通的第二凹部。 第二凹部比第一凹部大。 栅极电介质层形成在基板的顶表面上和第一凹槽和第二凹槽的内表面上。 第一多晶硅层填充第一凹槽并以第一杂质密度掺杂杂质。 第二多晶硅层填充第二凹槽，并以第二杂质密度掺杂杂质。 在第二多晶硅层内限定空隙。 在栅极电介质和第一多晶硅层上形成第三多晶硅层，并以第三杂质密度掺杂杂质。 由于在第二多晶硅层中存在杂质，可以基本上防止第二凹陷内的空隙的迁移。

公开(公告)号：US20060270215A1

公开(公告)日：2006-11-30

申请号：US11437625

申请日：2006-05-22

申请人： Kong-Soo Lee ,  Chang-Hoon Lee ,  Young-Sub You ,  Jung-Hwan Oh ,  Sang-Jin Park

发明人： Kong-Soo Lee ,  Chang-Hoon Lee ,  Young-Sub You ,  Jung-Hwan Oh ,  Sang-Jin Park

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/28525 ,  H01L21/28531 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

摘要： A semiconductor device and a method of manufacturing the semiconductor device may include a layered structure and a plug. The layered structure may have a lower insulation layer pattern, a single crystalline silicon pattern, and an upper insulation layer pattern provided on a substrate. A contact hole may be provided in the layered structure. The contact hole may expose the single crystalline silicon pattern and the substrate. The plug may include silicon germanium. The plug may be provided in the contact hole and may be electrically connected to the substrate and the single crystalline silicon pattern.

摘要翻译： 半导体器件和半导体器件的制造方法可以包括分层结构和插头。 层状结构可以具有较低的绝缘层图案，单晶硅图案和设置在基底上的上部绝缘层图案。 可以在层状结构中设置接触孔。 接触孔可以暴露单晶硅图案和衬底。 插头可以包括硅锗。 插头可以设置在接触孔中，并且可以电连接到衬底和单晶硅图案。

公开(公告)号：US20100323489A1

公开(公告)日：2010-12-23

申请号：US12805825

申请日：2010-08-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L21/02

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

公开(公告)号：US08241979B2

公开(公告)日：2012-08-14

申请号：US12805825

申请日：2010-08-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L21/8234

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

摘要翻译： 形成垂直二极管的方法和制造半导体器件（例如，诸如相变存储器件的半导体存储器件）的方法包括：在衬底上形成具有开口的绝缘结构，并用非晶硅填充该开口 层。 形成金属硅化物层以接触非晶硅层的至少一部分，然后通过使用金属硅化物层使非晶硅层结晶而在开口中形成多晶硅层。 通过将杂质注入到多晶硅层中形成掺杂多晶硅层。 因此，在开口中形成多晶硅层，而不进行选择性外延生长（SEG）工艺，从而可以提高二极管的电特性。

公开(公告)号：US07803679B2

公开(公告)日：2010-09-28

申请号：US12034440

申请日：2008-02-20

申请人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

发明人： Sang-Jin Park ,  Kong-Soo Lee ,  Yong-Woo Hyung ,  Young-Sub You ,  Jae-Jong Han

IPC分类号： H01L29/88

CPC分类号： H01L45/143 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02672 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/66204 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

摘要翻译： 形成垂直二极管的方法和制造半导体器件（例如，诸如相变存储器件的半导体存储器件）的方法包括：在衬底上形成具有开口的绝缘结构，并用非晶硅填充该开口 层。 形成金属硅化物层以接触非晶硅层的至少一部分，然后通过使用金属硅化物层使非晶硅层结晶而在开口中形成多晶硅层。 通过将杂质注入到多晶硅层中形成掺杂多晶硅层。 因此，在开口中形成多晶硅层，而不进行选择性外延生长（SEG）工艺，从而可以提高二极管的电特性。

公开(公告)号：US20070022941A1

公开(公告)日：2007-02-01

申请号：US11494566

申请日：2006-07-28

申请人： Jae-Young Park ,  Young-Jin Kim ,  Yong-Woo Hyung ,  Seok-Woo Nam ,  Kyoung-Seok Kim ,  Wook-Yeol Yi ,  Hun-Hyeoung Leam ,  Kong-Soo Lee ,  Ko-Eun Lee

发明人： Jae-Young Park ,  Young-Jin Kim ,  Yong-Woo Hyung ,  Seok-Woo Nam ,  Kyoung-Seok Kim ,  Wook-Yeol Yi ,  Hun-Hyeoung Leam ,  Kong-Soo Lee ,  Ko-Eun Lee

IPC分类号： C30B15/14

CPC分类号： C30B29/06 ,  C30B1/023

摘要： In a method of forming a layer having a lower electrical resistance and a method of manufacturing a semiconductor device, a first layer may be formed on a single crystalline substrate using amorphous silicon doped with impurities. A heat treatment may be performed on the single crystalline substrate at a temperature of about 550° C. to about 600° C. to convert the first layer into a second layer including a single crystalline silicon film transformed from a lower portion of the first layer contacting the single crystalline substrate and a polysilicon film transformed from an upper portion of the first layer. The layer may be formed at a relatively low temperature by a selective epitaxial growth process, and thus degradation or damage to a semiconductor device, which may be generated in a high temperature process, may be reduced.

摘要翻译： 在形成具有较低电阻的层的方法和制造半导体器件的方法中，可以使用掺杂有杂质的非晶硅在单晶衬底上形成第一层。 可以在约550℃至约600℃的温度下对单晶衬底进行热处理，以将第一层转变成第二层，该第二层包括从第一层的下部变换的单晶硅膜 使所述单晶衬底和从所述第一层的上部变换的多晶硅膜接触。 可以通过选择性外延生长工艺在相对低的温度下形成该层，从而可以降低在高温过程中可能产生的对半导体器件的劣化或损坏。

公开(公告)号：US06881637B2

公开(公告)日：2005-04-19

申请号：US10672884

申请日：2003-09-26

申请人： Jae-Jong Han ,  Yong-Woo Hyung ,  Seung-Mok Shin ,  Kong-Soo Lee ,  Eun-Jung Yun

发明人： Jae-Jong Han ,  Yong-Woo Hyung ,  Seung-Mok Shin ,  Kong-Soo Lee ,  Eun-Jung Yun

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/28247 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837

摘要： In a method for forming a gate electrode having an excellent sidewall profile, after a gate structure is formed on a substrate, a first oxide film is formed on a sidewall of the gate structure and on the substrate by re-oxidizing the gate structure and the substrate under an atmosphere including an oxygen gas and an inert gas. The gate structure has a gate oxide film pattern, a polysilicon film pattern and a metal silicide film pattern. A portion of the first oxide film formed on a sidewall of the polysilicon film pattern has a thickness substantially identical to that of a portion of the first oxide film formed on a sidewall of the metal silicide film pattern. A failure of a semiconductor device having the gate electrode can be minimized because the gate electrode has an improved sidewall profile.

摘要翻译： 在形成具有优异的侧壁轮廓的栅电极的方法中，在基板上形成栅极结构之后，在栅极结构的侧壁和基板上形成第一氧化膜，通过重新氧化栅极结构和 在包含氧气和惰性气体的气氛下进行。 栅极结构具有栅极氧化膜图案，多晶硅膜图案和金属硅化物膜图案。 形成在多晶硅膜图案的侧壁上的第一氧化膜的一部分的厚度与形成在金属硅化物膜图案的侧壁上的第一氧化物膜的部分的厚度基本相同。 具有栅电极的半导体器件的故障可以最小化，因为栅电极具有改进的侧壁轮廓。

公开(公告)号：US07598141B2

公开(公告)日：2009-10-06

申请号：US11261266

申请日：2005-10-28

申请人： Chang-Hoon Lee ,  Sang-Jin Park ,  Won-Seok Yoo ,  Kong-Soo Lee

发明人： Chang-Hoon Lee ,  Sang-Jin Park ,  Won-Seok Yoo ,  Kong-Soo Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： A method of fabricating a static random access memory device includes selectively removing an insulating film and growing a single crystalline silicon layer using selective epitaxy growth, the single crystalline silicon layer being grown in a portion from which the insulating film is removed; recessing the insulating film; and depositing an amorphous silicon layer on the single crystalline silicon layer and the insulating film, such that the amorphous silicon layer partially surrounds a top surface and side surfaces of the single crystalline silicon layer.

摘要翻译： 一种制造静态随机存取存储器件的方法包括：使用选择性外延生长选择性地去除绝缘膜并生长单晶硅层，单晶硅层在除去绝缘膜的部分中生长; 使绝缘膜凹陷; 以及在所述单晶硅层和所述绝缘膜上沉积非晶硅层，使得所述非晶硅层部分地包围所述单晶硅层的顶表面和侧表面。

公开(公告)号：US20060108575A1

公开(公告)日：2006-05-25

申请号：US11261266

申请日：2005-10-28

申请人： Chang-Hoon Lee ,  Sang-Jin Park ,  Won-Seok Yoo ,  Kong-Soo Lee

发明人： Chang-Hoon Lee ,  Sang-Jin Park ,  Won-Seok Yoo ,  Kong-Soo Lee

IPC分类号： H01L29/08

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： A method of fabricating a static random access memory device includes selectively removing an insulating film and growing a single crystalline silicon layer using selective epitaxy growth, the single crystalline silicon layer being grown in a portion from which the insulating film is removed; recessing the insulating film; and depositing an amorphous silicon layer on the single crystalline silicon layer and the insulating film, such that the amorphous silicon layer partially surrounds a top surface and side surfaces of the single crystalline silicon layer.