公开(公告)号：US06317801B1

公开(公告)日：2001-11-13

申请号：US09123097

申请日：1998-07-27

申请人： Alper Ilkbahar ,  Kent R. Townley

发明人： Alper Ilkbahar ,  Kent R. Townley

IPC分类号： G06F300

CPC分类号： G06F13/4086

摘要： A method and apparatus for post-driving and pre-driving a terminated bus that shortens dead cycles on a bus during bus master change-overs. In one embodiment, a first bus agent giving up control of the bus drives the bus to termination voltage levels during a first portion of the dead cycle. A second bus agent gaining control of the bus also drives the bus to termination voltage levels during a last portion of the dead cycle. For the time period between the first portion and the second portion, termination components such as resistors or transistors maintain the bus at termination voltage levels. By driving the bus to termination voltage levels with bus agents, bus transients are settled more quickly than with termination components alone, which improves performance of the bus over configurations pulled to termination voltage levels with termination components alone.

摘要翻译： 一种用于后期驱动和预驱动终端总线的方法和装置，其在总线主机切换期间缩短总线上的死循环。 在一个实施例中，放弃对总线的控制的第一总线代理在总线周期的第一部分期间将总线驱动到终端电压电平。 获得对总线控制的第二总线代理也驱动总线在死循环的最后部分期间的终止电压电平。 对于第一部分和第二部分之间的时间段，诸如电阻器或晶体管的端接部件将总线保持在终止电压电平。 通过使用总线代理将总线驱动到终端电压电平，总线瞬变比单独使用终端组件更快地进行安装，这样可以提高总线的性能，而这种配置仅通过端接组件被拉至终端电压电平。

公开(公告)号：US06188260B1

公开(公告)日：2001-02-13

申请号：US09235189

申请日：1999-01-22

申请人： Dan Stotz ,  Raymond W Rosenberry ,  Kent R Townley ,  Gayvin E Stong

发明人： Dan Stotz ,  Raymond W Rosenberry ,  Kent R Townley ,  Gayvin E Stong

IPC分类号： H03K3289

CPC分类号： H03K3/0372

摘要： A master-slave flip-flop and method is provided for use with critical path circuits, for example, driving output pads on an integrated circuit. Briefly described, in architecture, the master-slave flip-flop comprises a master stage and a slave stage. The master stage includes a pass gate, an input inverter coupled to the pass gate, a feedback inverter coupled across the input inverter, and a driving inverter coupled to the output of the input inverter. The output of the driving inverter is coupled to the slave stage which includes a second pass gate through which the output of the driving inverter is applied to the master-slave flip-flop output. The above architecture results in a fast setup time and a fast clock-to-Q time without the problems associated with kickback. Also, the output of the master-slave flip-flop is tristatable.

摘要翻译： 主 - 从触发器和方法被提供用于关键路径电路，例如驱动集成电路上的输出焊盘。 简要描述，在架构中，主从触发器包括主站和从站。 主级包括通路，耦合到通路的输入反相器，耦合在输入反相器两端的反馈反相器和耦合到输入反相器的输出的驱动反相器。 驱动逆变器的输出耦合到从动级，该副级包括第二级通过栅极，驱动逆变器的输出通过该第二通道施加到主从触发器输出端。 上述架构导致快速建立时间和快速的时钟到Q时间，而没有与回扣相关的问题。 此外，主从触发器的输出也是可调整的。

公开(公告)号：US08996906B1

公开(公告)日：2015-03-31

申请号：US12960459

申请日：2010-12-03

申请人： Kent R. Townley ,  Christopher D. Ebeling ,  Hamish Fallside ,  Prasun K. Raha

发明人： Kent R. Townley ,  Christopher D. Ebeling ,  Hamish Fallside ,  Prasun K. Raha

IPC分类号： G06F1/04 ,  G06F1/10 ,  H03K19/00 ,  H03K19/173

CPC分类号： H03K19/17796 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  G06F17/5045 ,  G06F17/5054 ,  H03K19/00 ,  H03K19/173 ,  H03K19/1733 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774

摘要： A novel integrated circuit (IC) that configurably distributes clocks from multiple clock sources to multiple sets of circuits is described. The IC includes multiple clock sources and multiple clock domains. Each clock domain includes a clock signal and a control signal. The clock signal is configurably selected from one of the multiple clock sources. The control signal is synchronized to the clock signal. The IC also includes multiple configurable circuits. A configurable circuit can configurably operate in one of the clock domains by selecting and using the control signal and the clock signal of the clock domain.

摘要翻译： 描述了一种从多个时钟源将时钟配置分配到多组电路的新型集成电路（IC）。 该IC包括多个时钟源和多个时钟域。 每个时钟域包括时钟信号和控制信号。 时钟信号可从多个时钟源之一配置选择。 控制信号与时钟信号同步。 IC还包括多个可配置电路。 通过选择和使用时钟域的控制信号和时钟信号，可配置的电路可以在时钟域之一中配置运行。

公开(公告)号：US06300822B1

公开(公告)日：2001-10-09

申请号：US09104921

申请日：1998-06-25

申请人： Brian Cardanha ,  Dan Stotz ,  Kent R. Townley

发明人： Brian Cardanha ,  Dan Stotz ,  Kent R. Townley

IPC分类号： G05F110

CPC分类号： G05F1/467

摘要： The inventive mechanism provides a hysteresis margin to a comparator. The inventive mechanism generates two different voltage values, one high level and one low level, which forms the noise margin. The mechanism will select the proper level based on the output of the comparator. The comparator will then use the selected reference voltage, having either a slightly higher or lower level than a nominal reference value, as the reference voltage in its operations. The difference between each level and the nominal level is the added hysteresis noise margin. The inventive mechanism uses the higher voltage level when the output of the comparator is below the nominal reference voltage, and uses the lower voltage level when the output of the comparator is above the nominal reference voltage. Thus, a noise spike in the input signal would have to be larger than the margin provided by the mechanism, before causing the comparator to react to the noise in the signal. Since the mechanism is separate from the comparator, different comparators do not have be designed and tested. The mechanism can be disabled by a shorting some of the nodes of the mechanism together during the metal layer step of the device fabrication.

摘要翻译： 本发明的机构向比较器提供滞后余量。 本发明机构产生形成噪声容限的两个不同的电压值，一个高电平和一个低电平。 该机制将根据比较器的输出选择适当的电平。 然后比较器将使用所选择的参考电压作为其运行中的参考电压，具有比标称参考值略高或更低的电平。 每个电平和额定电平之间的差值是增加的滞后噪声容限。 当比较器的输出低于额定参考电压时，本发明的机构使用较高的电压电平，并且当比较器的输出高于标称参考电压时使用较低的电压电平。 因此，在使比较器对信号中的噪声作出反应之前，输入信号中的噪声尖峰将必须大于由该机构提供的余量。 由于该机制与比较器分离，因此不需要对不同的比较器进行设计和测试。 可以通过在器件制造的金属层步骤期间将机构的一些节点一起短路来禁用该机制。

公开(公告)号：US6069512A

公开(公告)日：2000-05-30

申请号：US997768

申请日：1997-12-24

申请人： Pablo Martin Rodriguez ,  Kent R. Townley

发明人： Pablo Martin Rodriguez ,  Kent R. Townley

IPC分类号： H03K3/012 ,  H03K3/356

CPC分类号： H03K17/063 ,  H03K17/04163 ,  H03K3/012 ,  H03K3/356121 ,  H03K2217/0036

摘要： A half latch for latching a voltage at a domino gate output with reduced crossbar current duty cycle, comprising a CMOS inverter with input connected to the domino gate output, a first pMOSFET having a gate and drain connected to ground and having a source coupled to the source of the nMOSFET of the CMOS inverter to prevent the source voltage of the nMOSFET from approaching ground, and a second pMOSFET having a gate connected to the output of the CMOS inverter and having a drain connected to the input of the CMOS inverter.

摘要翻译： 半锁存器，用于以减小的交叉电流占空比在多米诺骨牌输出端锁存电压，包括具有连接到多米诺式输出端的输入的CMOS反相器，第一pMOSFET，其栅极和漏极连接到地并具有耦合到 CMOS反相器的nMOSFET的源极，以防止nMOSFET的源极电压接近接地;以及第二pMOSFET，其栅极连接到CMOS反相器的输出，并且具有连接到CMOS反相器的输入的漏极。

公开(公告)号：US06703882B1

公开(公告)日：2004-03-09

申请号：US09392341

申请日：1999-09-08

申请人： Pablo Martin Rodriguez ,  Kent R. Townley

发明人： Pablo Martin Rodriguez ,  Kent R. Townley

IPC分类号： H03K3356

CPC分类号： H03K17/063 ,  H03K3/012 ,  H03K3/356121 ,  H03K17/04163 ,  H03K2217/0036

摘要： A half latch for latching a voltage at a domino gate output with reduced crossbar current duty cycle, comprising a CMOS inverter with input connected to the domino gate output, a first pMOSFET having a gate and drain connected to ground and having a source coupled to the source of the nMOSFET of the CMOS inverter to prevent the source voltage of the nMOSFET from approaching ground, and a second pMOSFET having a gate connected to the output of the CMOS inverter and having a drain connected to the input of the CMOS inverter.

摘要翻译： 半锁存器，用于以减小的交叉电流占空比在多米诺骨牌输出端锁存电压，包括具有连接到多米诺式输出端的输入的CMOS反相器，第一pMOSFET，其栅极和漏极连接到地并具有耦合到 CMOS反相器的nMOSFET的源极，以防止nMOSFET的源极电压接近地，以及第二pMOSFET，其栅极连接到CMOS反相器的输出，并且具有连接到CMOS反相器的输入端的漏极。

公开(公告)号：US06535989B1

公开(公告)日：2003-03-18

申请号：US09471462

申请日：1999-12-22

申请人： Josef A Dvorak ,  Ricky L Pettit ,  David B Hollenbeck ,  Kent R Townley

发明人： Josef A Dvorak ,  Ricky L Pettit ,  David B Hollenbeck ,  Kent R Townley

IPC分类号： G06F104

CPC分类号： H03K5/1504 ,  G06F1/08 ,  H03L7/0812 ,  H03L7/0996 ,  H03L7/16

摘要： An apparatus for producing one or more clock signals comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A clock signal fed through the plurality of delay elements produces multiple delayed versions of the clock signal. Logic circuitry selects and combines the delayed clock signal versions to produce one or more output clock signals, each having a frequency that is a selected fraction of the input clock signal. An associated method delays the input clock signal N times sequentially for a natural number N. then selects a series of time splices of the delayed clock signals to produce an output clock signal. In some implementations the input clock signal can be referenced to a reference clock signal. The output clock signal frequency can be set to (N/M)×fref, for a natural number M and reference clock signal frequency fref. The apparatus and associated method can flexibly produce a large variety of output clock frequencies and frequency ratios, lock to fref with a dynamic response independent of the output frequency range and can be optimized to a single reference frequency, need not relock to change output frequency, and reduce clock skew.

摘要翻译： 用于产生一个或多个时钟信号的装置包括顺序连接的多个延迟元件和连接到多个延迟元件中的若干个的逻辑电路。 通过多个延迟元件馈送的时钟信号产生时钟信号的多个延迟版本。 逻辑电路选择和组合延迟的时钟信号版本以产生一个或多个输出时钟信号，每个输出时钟信号具有作为输入时钟信号的选定分数的频率。 相关联的方法对自然数N依次延迟输入时钟信号N，然后选择延迟的时钟信号的一系列时间接合以产生输出时钟信号。 在一些实现中，输入时钟信号可以参考参考时钟信号。 对于自然数M和参考时钟信号频率fref，输出时钟信号频率可以设置为（N / M）xfref。 该装置和相关方法可以灵活地产生各种各样的输出时钟频率和频率比，利用独立于输出频率范围的动态响应锁定到fref，并且可以优化到单个参考频率，不需要重新锁定来改变输出频率， 并减少时钟偏差。