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    Resistive memory devices, circuits and methods having read current limiting
    1.
    发明授权
    Resistive memory devices, circuits and methods having read current limiting 有权
    具有读取电流限制的电阻式存储器件，电路和方法

    公开(公告)号：US09165648B1

    公开(公告)日：2015-10-20

    申请号：US13336642

    申请日：2011-12-23

    申请人： John Ross Jameson, III

    发明人： John Ross Jameson, III

    IPC分类号： G11C17/00 ,  G11C13/00

    CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/76

    摘要： A memory device, comprising: read circuits coupled to a plurality of memory elements programmable between at least two different resistance states, the read circuits generating output values based on resistance states of selected memory elements in a read operation; and current limit circuits that limit a current flow through each memory element to less than a program threshold current; wherein the program threshold current corresponds to a current that flows through a memory element being programmed to cause its resistance to change to a resistance between that of two different resistance states.

    摘要翻译： 一种存储器件，包括：耦合到在至少两个不同电阻状态之间可编程的多个存储器元件的读取电路，所述读取电路在读取操作中基于所选择的存储器元件的电阻状态产生输出值; 以及电流限制电路，其将通过每个存储器元件的电流限制为小于编程阈值电流; 其中所述程序阈值电流对应于流过正被编程以使其电阻改变为两个不同电阻状态之间的电阻的存储器元件的电流。

    Programmable window of operation for CBRAM
    2.
    发明授权
    Programmable window of operation for CBRAM 有权
    可编程CBRAM操作窗口

    公开(公告)号：US09047948B1

    公开(公告)日：2015-06-02

    申请号：US13548429

    申请日：2012-07-13

    申请人： John Dinh ,  Nad Edward Gilbert ,  Shane Hollmer ,  Derric Lewis ,  John Ross Jameson ,  Daniel C. Wang ,  Juan Pablo Saenz Echeverry

    发明人： John Dinh ,  Nad Edward Gilbert ,  Shane Hollmer ,  Derric Lewis ,  John Ross Jameson ,  Daniel C. Wang ,  Juan Pablo Saenz Echeverry

    IPC分类号： G11C11/00 ,  G11C13/00

    CPC分类号： G11C13/0069 ,  G11C11/5614 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0097

    摘要： Structures and methods for control of an operating window of a programmable impedance element are disclosed herein. In one embodiment, a semiconductor memory device can include: (i) a memory array having a programmable impedance element; (ii) a register configured to be programmed with data that represents an erase verify value, a program verify value, and a read trip point resistance value, for the memory array; (iii) a controller configured to determine a mode of operation for the memory array; (iv) a register access circuit configured to read the register to obtain data that corresponds to the mode of operation; and (v) a voltage generator configured to generate a reference voltage based on the register data, where the reference voltage is used to perform an operation on the programmable impedance element corresponding to the mode of operation.

    摘要翻译： 本文公开了用于控制可编程阻抗元件的操作窗口的结构和方法。 在一个实施例中，半导体存储器件可以包括：（i）具有可编程阻抗元件的存储器阵列; （ii）配置为对存储器阵列编程的表示擦除验证值，程序验证值和读取跳变点电阻值的寄存器; （iii）控制器，被配置为确定所述存储器阵列的操作模式; （iv）寄存器访问电路，被配置为读取所述寄存器以获得对应于所述操作模式的数据; 以及（v）电压发生器，被配置为基于所述寄存器数据产生参考电压，其中所述参考电压用于对与所述操作模式相对应的所述可编程阻抗元件执行操作。

    Read methods, circuits and systems for memory devices
    5.
    发明授权
    Read methods, circuits and systems for memory devices 有权
    读取存储器件的方法，电路和系统

    公开(公告)号：US08654561B1

    公开(公告)日：2014-02-18

    申请号：US13276763

    申请日：2011-10-19

    申请人： John Ross Jameson ,  John Dinh ,  Derric Lewis ,  Daniel Wang ,  Shane Charles Hollmer ,  Nad Edward Gilbert ,  Janet Wang

    发明人： John Ross Jameson ,  John Dinh ,  Derric Lewis ,  Daniel Wang ,  Shane Charles Hollmer ,  Nad Edward Gilbert ,  Janet Wang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1673 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061

    摘要： A memory device can include a plurality of programmable elements; at least one sense circuit that generates sense data values from detected impedances of accessed programmable elements; and at least one data store circuit that stores initial data values from the at least one sense circuit, and stores output data values from the at least one sense circuit after check conditions have been applied to at least one programmable element. The check conditions can induce a change in impedance for programmable elements programmed to at least one predetermined state. Methods can include reading data from at least one memory cell of a memory device comprising a plurality of such memory cells; if the read data has a first value, providing such data as an output value; and if the read data has a second value, repeating access to the memory cell to confirm the read data value.

    摘要翻译： 存储器件可以包括多个可编程元件; 至少一个感测电路，其从所访问的可编程元件的检测到的阻抗产生感测数据值; 以及至少一个数据存储电路，其存储来自所述至少一个感测电路的初始数据值，并且在检查条件已应用于至少一个可编程元件之后存储来自所述至少一个感测电路的输出数据值。 检查条件可以引起编程为至少一个预定状态的可编程元件的阻抗变化。 方法可以包括从包括多个这样的存储器单元的存储器件的至少一个存储器单元读取数据; 如果读取的数据具有第一值，则提供这样的数据作为输出值; 并且如果读取的数据具有第二值，则重复访问存储器单元以确认读取的数据值。

    Variable impedance memory element structures, methods of manufacture, and memory devices containing the same
    8.
    发明授权
    Variable impedance memory element structures, methods of manufacture, and memory devices containing the same 失效
    可变阻抗存储元件结构，制造方法和包含该可变阻抗存储元件结构的存储器件

    公开(公告)号：US08624219B1

    公开(公告)日：2014-01-07

    申请号：US13445389

    申请日：2012-04-12

    申请人： John Ross Jameson ,  Antonio R. Gallo ,  Foroozan Sarah Koushan ,  Michael A. Van Buskirk

    发明人： John Ross Jameson ,  Antonio R. Gallo ,  Foroozan Sarah Koushan ,  Michael A. Van Buskirk

    IPC分类号： H01L47/00

    CPC分类号： H01L45/085 ,  H01L45/122

    摘要： A memory device can include at least one cathode formed in first opening of a first insulating layer; at least one anode formed in a second opening of second insulating layer, the second insulating layer being a different vertical layer than the first insulating layer; and a memory layer comprising an ion conductor layer extending laterally between the at least one anode and cathode on the first insulating layer, the ion conductor layer having a thickness in the vertical direction less than a depth of the first opening.

    摘要翻译： 存储器件可以包括形成在第一绝缘层的第一开口中的至少一个阴极; 形成在第二绝缘层的第二开口中的至少一个阳极，所述第二绝缘层是与所述第一绝缘层不同的垂直层; 以及存储层，其包括在所述第一绝缘层上的所述至少一个阳极和阴极之间横向延伸的离子导体层，所述离子导体层的垂直方向的厚度小于所述第一开口的深度。