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    Programmable window of operation for CBRAM
    1.
    发明授权
    Programmable window of operation for CBRAM 有权
    可编程CBRAM操作窗口

    公开(公告)号：US09047948B1

    公开(公告)日：2015-06-02

    申请号：US13548429

    申请日：2012-07-13

    申请人： John Dinh ,  Nad Edward Gilbert ,  Shane Hollmer ,  Derric Lewis ,  John Ross Jameson ,  Daniel C. Wang ,  Juan Pablo Saenz Echeverry

    发明人： John Dinh ,  Nad Edward Gilbert ,  Shane Hollmer ,  Derric Lewis ,  John Ross Jameson ,  Daniel C. Wang ,  Juan Pablo Saenz Echeverry

    IPC分类号： G11C11/00 ,  G11C13/00

    CPC分类号： G11C13/0069 ,  G11C11/5614 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0097

    摘要： Structures and methods for control of an operating window of a programmable impedance element are disclosed herein. In one embodiment, a semiconductor memory device can include: (i) a memory array having a programmable impedance element; (ii) a register configured to be programmed with data that represents an erase verify value, a program verify value, and a read trip point resistance value, for the memory array; (iii) a controller configured to determine a mode of operation for the memory array; (iv) a register access circuit configured to read the register to obtain data that corresponds to the mode of operation; and (v) a voltage generator configured to generate a reference voltage based on the register data, where the reference voltage is used to perform an operation on the programmable impedance element corresponding to the mode of operation.

    摘要翻译： 本文公开了用于控制可编程阻抗元件的操作窗口的结构和方法。 在一个实施例中，半导体存储器件可以包括：（i）具有可编程阻抗元件的存储器阵列; （ii）配置为对存储器阵列编程的表示擦除验证值，程序验证值和读取跳变点电阻值的寄存器; （iii）控制器，被配置为确定所述存储器阵列的操作模式; （iv）寄存器访问电路，被配置为读取所述寄存器以获得对应于所述操作模式的数据; 以及（v）电压发生器，被配置为基于所述寄存器数据产生参考电压，其中所述参考电压用于对与所述操作模式相对应的所述可编程阻抗元件执行操作。

    Circuits and methods for placing programmable impedance memory elements in high impedance states
    5.
    发明授权
    Circuits and methods for placing programmable impedance memory elements in high impedance states 有权
    将可编程阻抗存储器元件置于高阻态中的电路和方法

    公开(公告)号：US09368198B1

    公开(公告)日：2016-06-14

    申请号：US14281830

    申请日：2014-05-19

    申请人： Deepak Kamalanathan ,  Juan Pablo Saenz Echeverry ,  Venkatesh P. Gopinath

    发明人： Deepak Kamalanathan ,  Juan Pablo Saenz Echeverry ,  Venkatesh P. Gopinath

    IPC分类号： G11C11/00 ,  G11C13/00

    CPC分类号： G11C13/0011 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073

    摘要： A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor configured to enable a program current to flow through at least one memory element in response to the application of a program signal at its control terminal and a program bias voltage to the memory element; and an erase load circuit that includes at least one two-terminal diode-like load element, the erase load circuit configured to enable an erase current to flow through the load element and at least one memory element in a direction opposite to that of the program current.

    摘要翻译： 存储器件可以包括多个两端导电桥接随机存取存储器（CBRAM）型存储器元件; 至少一个程序晶体管被配置为响应于在其控制端处应用程序信号而使程序电流流过至少一个存储器元件，并且将程序偏置电压提供给存储器元件; 以及擦除负载电路，其包括至少一个二端二极管状负载元件，所述擦除负载电路被配置为使得擦除电流能够以与所述程序相反的方向流过所述负载元件和至少一个存储元件 当前。

    CBRAM/ReRAM with improved program and erase algorithms
    7.
    发明授权
    CBRAM/ReRAM with improved program and erase algorithms 有权
    CBRAM / ReRAM具有改进的编程和擦除算法

    公开(公告)号：US08659954B1

    公开(公告)日：2014-02-25

    申请号：US13548470

    申请日：2012-07-13

    申请人： Derric Lewis ,  Shane Hollmer ,  Vasudevan Gopalakrishnan ,  John Dinh ,  Foroozan Sarah Koushan ,  Juan Pablo Saenz Echeverry

    发明人： Derric Lewis ,  Shane Hollmer ,  Vasudevan Gopalakrishnan ,  John Dinh ,  Foroozan Sarah Koushan ,  Juan Pablo Saenz Echeverry

    IPC分类号： G11C7/00

    CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0092

    摘要： Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of controlling a programmable impedance element can include: (i) receiving a program or erase command to be executed on the programmable impedance element; (ii) selecting an operation algorithm for executing the command, where the operation algorithm is selected from among a plurality of operation algorithms by decoding at least two bits stored in a register; (iii) determining, using the register, a plurality of option variables for the selected operation algorithm, where the option variables are used to set conditions for one or more of a plurality of program and erase operations of the selected operation algorithm; and (iv) executing the command on the programmable impedance element by performing the one or more of the plurality of program and erase operations of the selected operation algorithm.

    摘要翻译： 本文公开了用于控制可编程阻抗元件的操作的结构和方法。 在一个实施例中，控制可编程阻抗元件的方法可以包括：（i）接收要在可编程阻抗元件上执行的编程或擦除命令; （ii）选择用于执行命令的操作算法，其中通过解码存储在寄存器中的至少两个比特来从多个操作算法中选择操作算法; （iii）使用所述寄存器确定用于所选择的操作算法的多个选项变量，其中所述选项变量用于设置所选择的操作算法的多个编程和擦除操作中的一个或多个的条件; 以及（iv）通过执行所选择的操作算法的多个编程和擦除操作中的一个或多个来执行在可编程阻抗元件上的命令。