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    APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS
    1.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS 有权
    使用隧道场效应晶体管的DENSE电路的装置，方法和系统

    公开(公告)号：US20160182023A1

    公开(公告)日：2016-06-23

    申请号：US14575962

    申请日：2014-12-18

    申请人： Daniel H. Morris ,  Uygar E. Avci ,  Rafael Rios ,  Ian A. Young

    发明人： Daniel H. Morris ,  Uygar E. Avci ,  Rafael Rios ,  Ian A. Young

    IPC分类号： H03K3/356 ,  G11C11/419

    CPC分类号： G11C11/419 ,  G11C5/145 ,  G11C11/412 ,  H01L27/1104 ,  H03K3/356104

    摘要： Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.

    摘要翻译： 实施例包括用于移位电压电平的电路的装置，方法和系统。 电路可以包括第一反相器，其包括耦合以传递低电压信号的第一晶体管和耦合以接收低电压信号的第二反相器。 电路还可以包括第二晶体管，其被耦合以从第二反相器接收低电压信号，以用作反馈装置并产生高电压信号。 在实施例中，第一晶体管不对称地导通，以防止高电压信号到低电压域的交叉。 还描述了低电压存储器阵列。 在实施例中，用于移位电压电平的电路可以有助于包括低电压域的低电压存储器阵列和高电压域的逻辑分量的逻辑组件之间的通信。 还可以描述另外的实施例。

    Chainlink memory
    2.
    发明授权
    Chainlink memory 有权
    链式记忆

    公开(公告)号：US09117523B1

    公开(公告)日：2015-08-25

    申请号：US13649989

    申请日：2012-10-11

    申请人： Daniel H. Morris ,  David M. Bromberg ,  Lawrence T. Pileggi ,  Jiam-Gang (Jimmy) Zhu

    发明人： Daniel H. Morris ,  David M. Bromberg ,  Lawrence T. Pileggi ,  Jiam-Gang (Jimmy) Zhu

    IPC分类号： G11C19/00 ,  G11C19/02

    CPC分类号： G11C19/0841 ,  G11C11/161 ,  G11C11/1675 ,  G11C19/08 ,  G11C19/0808 ,  G11C2213/71

    摘要： A nonvolatile alternative to DRAM or Flash is disclosed. It involves a new “magnetic shift register” that avoids the bit annihilation problem that plagues magnetic racetrack memories. Using this new “chainlink memory” approach, one avoids the annihilation problem inherent in racetrack memory by breaking up the racetrack into magnetically coupled links, where each link preferably handles one bit exclusively. Depending upon the implementation, the “bit” can be, for example, the magnetization of a link, presence or absence of a domain wall, or the polarity of a domain wall. Numerous examples and applications of this new chainlink technology are disclosed.

    摘要翻译： 公开了DRAM或闪存的非易失性替代方案。 它涉及一个新的“磁移位寄存器”，避免了磁场赛马记忆的湮灭问题。 使用这种新的“链式记忆”方法，通过将跑道分解成磁耦合链路，避免了赛道内存中固有的湮灭问题，其中每个链路优选地仅处理一个比特。 根据实施方式，“位”可以是例如链路的磁化，域壁的存在或不存在或域壁的极性。 披露了这种新型链链技术的许多实例和应用。

    MEMORY DEVICES BASED ON CAPACITORS WITH BUILT-IN ELECTRIC FIELD
    3.
    发明申请
    MEMORY DEVICES BASED ON CAPACITORS WITH BUILT-IN ELECTRIC FIELD 审中-公开

    公开(公告)号：US20190393232A1

    公开(公告)日：2019-12-26

    申请号：US16016375

    申请日：2018-06-22

    申请人： Sou-Chi CHANG ,  Uygar E. AVCI ,  Daniel H. MORRIS ,  Seiyon KIM ,  Ashish V. PENUMATCHA ,  Ian A. YOUNG

    发明人： Sou-Chi CHANG ,  Uygar E. AVCI ,  Daniel H. MORRIS ,  Seiyon KIM ,  Ashish V. PENUMATCHA ,  Ian A. YOUNG

    IPC分类号： H01L27/11507 ,  H01L49/02 ,  G11C11/22

    摘要： Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.