公开(公告)号：US20160322360A1

公开(公告)日：2016-11-03

申请号：US15209622

申请日：2016-07-13

申请人： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

发明人： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC分类号： H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/108 ,  H01L29/49

CPC分类号： H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which alloys the different oxide and gate materials to he fabricated is described.

摘要翻译： 描述了一种用于制造浮体记忆单元（FBC）的方法，并且使用其中使用有利于不同导电类型区域的栅极的所得FBC。 在一个实施例中，具有更厚绝缘的p型背栅与较薄绝缘的n型前门一起使用。 描述了补偿其制造的不同氧化物和栅极材料合金的未对准的处理。

公开(公告)号：US20160155742A1

公开(公告)日：2016-06-02

申请号：US15017432

申请日：2016-02-05

申请人： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

发明人： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/06 ,  H01L29/49

CPC分类号： H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which alloys the different oxide and gate materials to he fabricated is described.

公开(公告)号：US20090003050A1

公开(公告)日：2009-01-01

申请号：US11772191

申请日：2007-06-30

申请人： Uygar E. Avci ,  Peter L.D. Chang ,  Dinesh Somasekhar

发明人： Uygar E. Avci ,  Peter L.D. Chang ,  Dinesh Somasekhar

IPC分类号： G11C11/34

CPC分类号： G11C7/02 ,  G11C11/404 ,  G11C2211/4016

摘要： Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.

摘要翻译： 本文提供了用于在阵列中的所选浮体单元的通道上施加冲击电离电位的布局的实施例，而不必将电位施加在其它未选择的单元上。

公开(公告)号：US09520399B2

公开(公告)日：2016-12-13

申请号：US15209622

申请日：2016-07-13

申请人： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

发明人： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L27/12 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US08569812B2

公开(公告)日：2013-10-29

申请号：US13534985

申请日：2012-06-27

申请人： Peter L. D. Chang ,  Uygar E. Avci ,  David L. Kencke ,  Ibrahim Ban

发明人： Peter L. D. Chang ,  Uygar E. Avci ,  David L. Kencke ,  Ibrahim Ban

IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L27/088 ,  H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US07652910B2

公开(公告)日：2010-01-26

申请号：US11772191

申请日：2007-06-30

申请人： Uygar E. Avci ,  Peter L. D. Chang ,  Dinesh Somasekhar

发明人： Uygar E. Avci ,  Peter L. D. Chang ,  Dinesh Somasekhar

IPC分类号： G11C11/24

CPC分类号： G11C7/02 ,  G11C11/404 ,  G11C2211/4016

摘要： Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.

摘要翻译： 本文提供了用于在阵列中的所选浮体单元的通道上施加冲击电离电位的布局的实施例，而不必将电位施加在其它未选择的单元上。

公开(公告)号：US20190393232A1

公开(公告)日：2019-12-26

申请号：US16016375

申请日：2018-06-22

申请人： Sou-Chi CHANG ,  Uygar E. AVCI ,  Daniel H. MORRIS ,  Seiyon KIM ,  Ashish V. PENUMATCHA ,  Ian A. YOUNG

发明人： Sou-Chi CHANG ,  Uygar E. AVCI ,  Daniel H. MORRIS ,  Seiyon KIM ,  Ashish V. PENUMATCHA ,  Ian A. YOUNG

IPC分类号： H01L27/11507 ,  H01L49/02 ,  G11C11/22

摘要： Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.

公开(公告)号：US09646970B2

公开(公告)日：2017-05-09

申请号：US15349862

申请日：2016-11-11

申请人： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

发明人： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

CPC分类号： H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20170084326A1

公开(公告)日：2017-03-23

申请号：US15126255

申请日：2014-07-08

申请人： Daniel H. Morris ,  Uygar E. Avci ,  Rafael Rios ,  Ian A. Young

发明人： Daniel H. Morris ,  Uygar E. Avci ,  Rafael Rios ,  Ian A. Young

IPC分类号： G11C11/38 ,  H01L27/105 ,  H01L27/102 ,  G11C11/412

CPC分类号： G11C11/38 ,  G11C11/404 ,  G11C11/412 ,  H01L27/102 ,  H01L27/1021 ,  H01L27/1052 ,  H01L29/7391 ,  H01L29/885

摘要： Described is a memory bit-cell comprising: a storage node; an access transistor coupled to the storage node; a capacitor having a first terminal coupled to the storage node; and one or more negative differential resistance devices coupled to the storage node such that the memory bit-cell is without one of a ground line or a supply line or both.

公开(公告)号：US08890120B2

公开(公告)日：2014-11-18

申请号：US13678867

申请日：2012-11-16

申请人： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, Jr. ,  Ian A. Young ,  Kelin J. Kuhn

发明人： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, Jr. ,  Ian A. Young ,  Kelin J. Kuhn

IPC分类号： H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

摘要翻译： 描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。 例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。 同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。 同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。 栅极堆叠包括栅极电介质部分和栅极电极部分。