公开(公告)号：US06194784B1

公开(公告)日：2001-02-27

申请号：US08976969

申请日：1997-11-24

申请人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

发明人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

IPC分类号： H01L2348

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： The encapsulation of gate stacks of a semiconductor device in an oxide insulative layer and in a silicon nitride etch-stop layer allows the formation of a contact filling for connection to underlying diffusion regions without risk of accidental diffusion contact to gate shorts created by the contact filling. As a result, the gate stacks may be patterned closer together, thus reducing the cell size and increasing the cell density. Furthermore, use of the etch-stop layer makes contact lithography easier since the size of the contact opening can be increased and contact alignment tolerance made less stringent without concern of increasing the cell size or of creating diffusion contact to gate shorts.

摘要翻译： 在氧化物绝缘层和氮化硅蚀刻停止层中封装半导体器件的栅极堆叠允许形成用于连接到下面的扩散区域的接触填充物，而不会发生与接触填充物产生的栅极短路的意外扩散接触的风险 。 结果，栅极堆叠可以被图案化在一起，从而减小电池尺寸并增加电池密度。 此外，使用蚀刻停止层使得接触光刻更容易，因为可以增加接触开口的尺寸并且接触对准公差变得不那么严格，而不考虑增加电池尺寸或产生与栅极短路的扩散接触。

公开(公告)号：US5731242A

公开(公告)日：1998-03-24

申请号：US557904

申请日：1995-11-14

申请人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

发明人： Krishna K. Parat ,  Glen N. Wada ,  Gregory E. Atwood ,  Daniel N. Tang

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/485 ,  H01L23/522 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002

摘要： The encapsulation of gate stacks of a semiconductor device in an oxide insulative layer and in a silicon nitride etch-stop layer allows the formation of a contact filling for connection to underlying diffusion regions without risk of accidental diffusion contact to gate shorts created by the contact filling. As a result, the gate stacks may be patterned closer together, thus reducing the cell size and increasing the cell density. Furthermore, use of the etch-stop layer makes contact lithography easier since the size of the contact opening can be increased and contact alignment tolerance made less stringent without concern of increasing the cell size or of creating diffusion contact to gate shorts.

摘要翻译： 在氧化物绝缘层和氮化硅蚀刻停止层中封装半导体器件的栅极堆叠允许形成用于连接到下面的扩散区域的接触填充物，而不会发生意外扩散接触到由接触填充物产生的栅极短路的风险 。 结果，栅极堆叠可以被图案化在一起，从而减小电池尺寸并增加电池密度。 此外，使用蚀刻停止层使得接触光刻更容易，因为可以增加接触开口的尺寸并且接触对准公差变得不那么严格，而不考虑增加电池尺寸或产生与栅极短路的扩散接触。

公开(公告)号：US5763912A

公开(公告)日：1998-06-09

申请号：US533404

申请日：1995-09-25

申请人： Krishna K. Parat ,  Gregory E. Atwood

发明人： Krishna K. Parat ,  Gregory E. Atwood

IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L29/76 ,  H01L29/792 ,  H01L29/94

CPC分类号： H01L27/115

摘要： A switching device having an electrically trimmable threshold voltage comprises a control transistor having favorable programming and erasing characteristics and a sensing transistor suited for stability and high drain voltages. The control transistor includes a floating gate for storing a charge. The control transistor receives an input voltage to vary the charge. The sensing transistor, which has a threshold voltage, includes the floating gate, which is formed from a single, contiguous layer of polysilicon or from separate polysilicon layers connected by metallization, such that the floating gate is shared by the control transistor and the sensing transistor. The control transistor has a tunnel oxide layer between a semiconductor layer and the floating gate having a thickness that is conducive to injection or tunneling of electrons through the tunnel oxide layer. The sensing transistor has a gate oxide layer between the semiconductor layer and the floating gate having a thickness greater than the thickness of the tunnel oxide layer, such as to substantially inhibit injection or tunneling of electrons through the gate oxide layer. Applying the input voltage to the control transistor varies the charge on the floating gate and thereby changes the threshold voltage of the sensing transistor.

摘要翻译： 具有电可调阈值电压的开关装置包括具有良好编程和擦除特性的控制晶体管和适用于稳定性和高漏极电压的感测晶体管。 控制晶体管包括用于存储电荷的浮动栅极。 控制晶体管接收输入电压以改变电荷。 具有阈值电压的感测晶体管包括浮置栅极，该栅极由单个相邻的多晶硅层或由通过金属化连接的单独的多晶硅层形成，使得浮置栅极由控制晶体管和感测晶体管共享 。 控制晶体管具有在半导体层和浮置栅极之间的隧道氧化物层，其厚度有利于电子通过隧道氧化物层的注入或隧穿。 感测晶体管具有在半导体层和浮置栅极之间的栅极氧化层，其厚度大于隧道氧化物层的厚度，例如基本上抑制电子通过栅极氧化物层的注入或隧穿。 将输入电压施加到控制晶体管会改变浮置栅极上的电荷，从而改变感测晶体管的阈值电压。

公开(公告)号：US5190887A

公开(公告)日：1993-03-02

申请号：US815946

申请日：1991-12-30

申请人： Daniel N. Tang ,  Gregory E. Atwood

发明人： Daniel N. Tang ,  Gregory E. Atwood

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/26586 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/7885

摘要： A method of forming a doped region within a monocrystalline silicon layer of an integrated circuit having an electrically erasable and electrically programmable memory device on a semiconductor substrate, wherein the doped region lies within a channel region near a drain region, but does not lie within a source region. After a patterned layer is formed over the channel region, the substrate is doped by ion implantation with a first dopant at a tilt angle no less than a minimum tilt angle and at about a predetermined azimuthal angle, such that a significant number of ions enter a drain region and a channel region near the drain region and substantially no ions enter a source region. The first dopant is the same dopant type as the monocrystalline silicon layer dopant. The drain region is masked. The source region is doped with a second dopant. The second dopant is an opposite dopant type as the monocrystalline silicon layer dopant. The source region and the drain region are doped with a third dopant. The third dopant is the same dopant type as the second dopant. The third dopant dose is heavier than the first dopant dose, and the second dopant diffusion coefficient is greater than the third dopant diffusion coefficient.

摘要翻译： 在半导体衬底上具有电可擦除和电可编程存储器件的集成电路的单晶硅层内形成掺杂区的方法，其中掺杂区位于漏区附近的沟道区内，但不在 源区。 在通道区域上形成图案层之后，通过离子注入掺杂衬底，以不小于最小倾斜角度和大约预定方位角的倾斜角以第一掺杂剂掺杂，使得大量离子进入 漏极区域和靠近漏极区域的沟道区域，并且基本上没有离子进入源极区域。 第一掺杂剂是与单晶硅层掺杂剂相同的掺杂剂类型。 漏极区域被掩蔽。 源区掺杂有第二掺杂剂。 第二掺杂剂是与单晶硅层掺杂剂相反的掺杂剂类型。 源极区和漏极区掺杂有第三掺杂剂。 第三掺杂剂是与第二掺杂剂相同的掺杂剂类型。 第三掺杂剂剂量比第一掺杂剂剂量重，第二掺杂剂扩散系数大于第三掺杂剂扩散系数。

公开(公告)号：US5729489A

公开(公告)日：1998-03-17

申请号：US572757

申请日：1995-12-14

申请人： Albert Fazio ,  Gregory E. Atwood ,  James O. Mi ,  Paul Ruby

发明人： Albert Fazio ,  Gregory E. Atwood ,  James O. Mi ,  Paul Ruby

IPC分类号： G11C11/56 ,  G11C11/34

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C2211/5625

摘要： A method for programming a memory cell having more than two possible states to a desired state. The method includes applying a programming pulse to the memory cell. The change in the amount of charge stored by the memory cell caused by applying the programming pulse to the memory cell is sensed. The control engine determines characterization information indicative of programming characteristics of the memory cell in response to the detected change in the amount of charge stored by the memory cell. The control engine then uses the characterization information to directly program the memory cell to approximately the desired state without performing a program verify operation.

摘要翻译： 一种用于将具有多于两种可能状态的存储单元编程到期望状态的方法。 该方法包括将编程脉冲施加到存储器单元。 感测到通过将编程脉冲施加到存储单元而由存储单元存储的电荷量的变化。 控制引擎响应于检测到的由存储器单元存储的电荷量的变化来确定指示存储器单元的编程特性的表征信息。 控制引擎然后使用表征信息直接将存储器单元编程到大致期望的状态，而不执行程序验证操作。

公开(公告)号：US5602794A

公开(公告)日：1997-02-11

申请号：US537233

申请日：1995-09-29

申请人： Jahanshir J. Javanifard ,  Kerry D. Tedrow ,  Jin-Lien Lin ,  Jeffrey J. Evertt ,  Gregory E. Atwood

发明人： Jahanshir J. Javanifard ,  Kerry D. Tedrow ,  Jin-Lien Lin ,  Jeffrey J. Evertt ,  Gregory E. Atwood

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  H02M3/07 ,  H02M3/28 ,  H03L7/089

CPC分类号： G11C16/30 ,  G11C5/145 ,  H02M3/07 ,  H02M2001/007 ,  H02M3/285

摘要： A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pumps are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.

摘要翻译： 描述了一种用于闪存器件的可变级电荷泵。 可变级电荷泵包括第一电荷泵和第二电荷泵。 第一开关将第一电荷泵的输出耦合到第二电荷泵的输入端。 第二开关将第一电荷泵的输入耦合到第二电荷泵的输入端。 当第一开关处于第一位置并且第二开关处于第二位置时，第一和第二电荷泵串联耦合到公共输出节点，其中第一和第二电荷泵并联耦合到公共输出节点 当第一开关处于第二位置并且第二开关处于第一位置时。

公开(公告)号：US5508958A

公开(公告)日：1996-04-16

申请号：US315292

申请日：1994-09-29

申请人： Albert Fazio ,  Gregory E. Atwood ,  Mark E. Bauer

发明人： Albert Fazio ,  Gregory E. Atwood ,  Mark E. Bauer

IPC分类号： G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C27/00 ,  G11C7/00

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C27/005 ,  G11C2211/5634 ,  G11C2211/5642 ,  G11C2211/5644 ,  G11C7/16

摘要： A method and apparatus for sensing the state of floating gate memory cells in a memory array. Because of its stability and accuracy, the sensing apparatus may be used for sensing the state of multi-bit floating gate memory cells. The state of a memory cell is sensed by applying a variable gate voltage to the top gate of the floating gate memory cell and comparing the cell current to a fixed reference current. A circuit detects when the cell current is equal to the reference current. When the currents are equal, the value of the variable gate voltage indicates the state of the memory cell. For one embodiment, an analog-to-digital converter converts the variable gate voltage to a digital value that is latched when the currents are equal. The latched digital value indicates the state of the memory cell. For this embodiment, a ramp voltage or other suitable variable voltage may be used as the variable gate voltage. For another embodiment, a digital-to-analog converter is used to generate the variable gate voltage. A counter generates digital values to step the variable gate voltage. When the cell current equals the fixed reference current, the digital counter value is latched to indicate the state of the memory cell.

摘要翻译： 一种用于感测存储器阵列中的浮动栅极存储器单元的状态的方法和装置。 由于其稳定性和精度，感测装置可以用于感测多位浮动栅极存储单元的状态。 通过向浮动栅极存储单元的顶栅施加可变栅极电压并将单元电流与固定参考电流进行比较来感测存储单元的状态。 电路检测电池电流何时等于参考电流。 当电流相等时，可变栅极电压的值表示存储单元的状态。 对于一个实施例，模数转换器将可变栅极电压转换成当电流相等时被锁存的数字值。 锁存的数字值表示存储单元的状态。 对于该实施例，可以使用斜坡电压或其它合适的可变电压作为可变栅极电压。 对于另一个实施例，使用数模转换器来产生可变栅极电压。 一个计数器产生数字值，以步进可变栅极电压。 当单元电流等于固定参考电流时，数字计数器值被锁存以指示存储单元的状态。

公开(公告)号：US5239505A

公开(公告)日：1993-08-24

申请号：US635308

申请日：1990-12-28

申请人： Albert Fazio ,  Gregory E. Atwood ,  Neal R. Mielke

发明人： Albert Fazio ,  Gregory E. Atwood ,  Neal R. Mielke

IPC分类号： G11C16/28 ,  G11C16/34

CPC分类号： G11C16/3431 ,  G11C16/28 ,  G11C16/3418

摘要： A non-volatile memory device is described. The memory device includes a first block and a second block. The first block includes a first memory cell having a drain region, a source region, a floating gate, and a control gate. A first word line is coupled to the control gate of the first memory cell. The second block includes a second memory cell having a drain region, a source region, a floating gate, and a control gate. A second word line is coupled to the control gate of the second memory cell. A bit line is coupled to the drain region of the first and the second memory cell. A refresh control means performs a refresh operation on one of the first and second memory cell. A sensing means is coupled to the bit line, and has a first reference potential and a second reference potential for detecting a voltage state of the first and second memory cell during the refresh operation. When the voltage state is detected to fall between the first reference potential and the second reference potential, the sensing means generates a refresh signal to the refresh control means. When the refresh control means receives the refresh signal from the sensing means, the voltage state is raised above the second reference potential. A method of refreshing the non-volatile device is also described.

摘要翻译： 描述非易失性存储器件。 存储器件包括第一块和第二块。 第一块包括具有漏极区域，源极区域，浮动栅极和控制栅极的第一存储单元。 第一字线耦合到第一存储器单元的控制栅极。 第二块包括具有漏极区域，源极区域，浮动栅极和控制栅极的第二存储单元。 第二字线耦合到第二存储单元的控制栅极。 位线耦合到第一和第二存储单元的漏极区域。 刷新控制装置对第一和第二存储单元之一执行刷新操作。 感测装置耦合到位线，并且具有用于在刷新操作期间检测第一和第二存储器单元的电压状态的第一参考电位和第二参考电位。 当检测到电压状态落在第一参考电位和第二参考电位之间时，感测装置向刷新控制装置产生刷新信号。 当刷新控制装置从感测装置接收到刷新信号时，电压状态升高到高于第二参考电位。 还描述了刷新非易失性设备的方法。

公开(公告)号：US08637342B2

公开(公告)日：2014-01-28

申请号：US11272208

申请日：2005-11-10

申请人： Ilya V. Karpov ,  Sean Jong Lee ,  Yudong Kim ,  Gregory E. Atwood

发明人： Ilya V. Karpov ,  Sean Jong Lee ,  Yudong Kim ,  Gregory E. Atwood

IPC分类号： H01L21/00

CPC分类号： H01L45/141 ,  G11C13/0004 ,  H01L27/2427 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

摘要： An ovonic threshold switch may be formed of a continuous chalcogenide layer. That layer spans multiple cells, forming a phase change memory. In other words, the ovonic threshold switch may be formed of a chalcogenide layer which extends, uninterrupted, over numerous cells of a phase change memory.

摘要翻译： 可以由连续的硫族化物层形成一个超声阈值开关。 该层跨越多个单元，形成相变存储器。 换句话说，超声阈值开关可以由在相变存储器的多个单元上不间断地延伸的硫族化物层形成。

公开(公告)号：US6091618A

公开(公告)日：2000-07-18

申请号：US910761

申请日：1997-08-13

申请人： Albert Fazio ,  Gregory E. Atwood ,  James Q. Mi

发明人： Albert Fazio ,  Gregory E. Atwood ,  James Q. Mi

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C27/00 ,  G11C13/00

CPC分类号： G11C27/005 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/565 ,  G11C2211/5621

摘要： A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

摘要翻译： 一种用于将存储器单元编程为至少三个电荷量之一的方法和电路。 通过增加施加到存储单元的编程脉冲的电压电平来增加放置在存储单元中的电荷量。