公开(公告)号：US06828180B2

公开(公告)日：2004-12-07

申请号：US10260067

申请日：2002-09-27

Applicant: Daniel Toet ,  Thomas W. Sigmon

Inventor： Daniel Toet ,  Thomas W. Sigmon

IPC: H01L2184

CPC classification number: H01L27/224 ,  B82Y10/00 ,  H01L29/861 ,  Y10S438/979

Abstract: A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Abstract translation: 用于直接集成薄膜硅p-n结二极管与磁性隧道结的方法，用于高性能，非易失性存储器阵列的高级磁随机存取存储器（MRAM）单元。 该方法基于用于在沉积到诸如陶瓷，电介质，玻璃或聚合物的低温基底上的金属的膜上制造垂直多晶硅电子器件结构，特别是p-n结二极管的脉冲激光处理。 该过程保留了典型地沉积器件的底层和结构，例如硅集成电路。 该方法涉及在金属层上的无定形或多晶相中的至少一层硅的低温沉积。 在沉积期间或之后，可以在硅膜中引入掺杂剂。 然后用有效吸收在硅中的短脉冲激光能量照射该膜，这导致膜的结晶并且同时通过超快熔化和固化来激活掺杂剂。 可以在结晶之前或之后对硅膜进行图案化。

公开(公告)号：US07468611B2

公开(公告)日：2008-12-23

申请号：US11875655

申请日：2007-10-19

Applicant: Kent Nguyen ,  Eric Thompson ,  Hai Tran ,  Kaushal Gangakhedkar ,  Robert Barnett ,  Daniel Toet ,  David Baldwin ,  Steve Aochi ,  Neil Nguyen

Inventor： Kent Nguyen ,  Eric Thompson ,  Hai Tran ,  Kaushal Gangakhedkar ,  Robert Barnett ,  Daniel Toet ,  David Baldwin ,  Steve Aochi ,  Neil Nguyen

IPC: G01R31/00 ,  G01R31/02

CPC classification number: G09G3/006 ,  G02F2001/136254

Abstract: A system performs continuous full linear scan of a flat media. The system includes, in part, a chuck, and at least first, second and third gantries. The chuck is adapted to support the flat media during the test. The first gantry includes at least one linear array of non-contacting sensors that spans the width of the flat media and is adapted to move across an entire length of the flat media. Each of the second and third gantries includes a probe head that spans the width of the flat media and each is adapted to apply an electrical signal to the flat media. Each probe head is further adapted to move along a direction substantially perpendicular to the surface of the flat media during the times when the first gantry is in motion and while test signals are being continuously applied.

Abstract translation: 系统执行平面介质的连续全线性扫描。 该系统部分地包括卡盘以及至少第一，第二和第三门架。 在测试期间卡盘适于支撑平面介质。 第一机架包括至少一个线性阵列的非接触式传感器，它们跨过平坦介质的宽度并且适于在平坦介质的整个长度上移动。 第二和第三门架中的每一个包括跨越平坦介质的宽度的探头，并且每个都适于将电信号施加到平坦介质。 每个探针头还适于在第一台架运动期间以及在连续施加测试信号的同时沿着基本上垂直于平坦介质的表面的方向移动。

公开(公告)号：US06541316B2

公开(公告)日：2003-04-01

申请号：US09746981

申请日：2000-12-22

Applicant: Daniel Toet ,  Thomas W. Sigmon

Inventor： Daniel Toet ,  Thomas W. Sigmon

IPC: H01L2100

CPC classification number: H01L27/224 ,  B82Y10/00 ,  H01L29/861 ,  Y10S438/979

Abstract: A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

公开(公告)号：US20080094081A1

公开(公告)日：2008-04-24

申请号：US11875655

申请日：2007-10-19

Applicant: Kent Nguyen ,  Eric Thompson ,  Hai Tran ,  Kaushal Gangakhedkar ,  Robert Barnett ,  Daniel Toet ,  David Baldwin ,  Steve Aochi ,  Neil Nguyen

Inventor： Kent Nguyen ,  Eric Thompson ,  Hai Tran ,  Kaushal Gangakhedkar ,  Robert Barnett ,  Daniel Toet ,  David Baldwin ,  Steve Aochi ,  Neil Nguyen

IPC: G01R31/302

CPC classification number: G09G3/006 ,  G02F2001/136254

Abstract: A system performs continuous full linear scan of a flat media. The system includes, in part, a chuck, and at least first, second and third gantries. The chuck is adapted to support the flat media during the test. The first gantry includes at least one linear array of non-contacting sensors that spans the width of the flat media and is adapted to move across an entire length of the flat media. Each of the second and third gantries includes a probe head that spans the width of the flat media and each is adapted to apply an electrical signal to the flat media. Each probe head is further adapted to move along a direction substantially perpendicular to the surface of the flat media during the times when the first gantry is in motion and while test signals are being continuously applied.

Abstract translation: 系统执行平面介质的连续全线性扫描。 该系统部分地包括卡盘以及至少第一，第二和第三门架。 在测试期间卡盘适于支撑平面介质。 第一机架包括至少一个线性阵列的非接触式传感器，它们跨过平坦介质的宽度并且适于在平坦介质的整个长度上移动。 第二和第三门架中的每一个包括跨越平坦介质的宽度的探头，并且每个都适于将电信号施加到平坦介质。 每个探针头还适于在第一台架运动期间以及在连续施加测试信号的同时沿着基本上垂直于平坦介质的表面的方向移动。

公开(公告)号：US06933530B2

公开(公告)日：2005-08-23

申请号：US10943475

申请日：2004-09-17

Applicant: Daniel Toet ,  Thomas W. Sigmon

Inventor： Daniel Toet ,  Thomas W. Sigmon

IPC: H01L21/8246 ,  H01L27/22 ,  H01L29/861 ,  H01L29/04

CPC classification number: H01L27/224 ,  B82Y10/00 ,  H01L29/861 ,  Y10S438/979

Abstract: A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Abstract translation: 用于直接集成薄膜硅p-n结二极管与磁性隧道结的方法，用于高性能，非易失性存储器阵列的高级磁随机存取存储器（MRAM）单元。 该方法基于用于在沉积到诸如陶瓷，电介质，玻璃或聚合物的低温基底上的金属的膜上制造垂直多晶硅电子器件结构，特别是p-n结二极管的脉冲激光处理。 该过程保留了典型地沉积器件的底层和结构，例如硅集成电路。 该方法涉及在金属层上的无定形或多晶相中的至少一层硅的低温沉积。 在沉积期间或之后，可以在硅膜中引入掺杂剂。 然后用有效吸收在硅中的短脉冲激光能量照射该膜，这导致膜的结晶并且同时通过超快熔化和固化来激活掺杂剂。 可以在结晶之前或之后对硅膜进行图案化。

公开(公告)号：US20050083729A1

公开(公告)日：2005-04-21

申请号：US10943475

申请日：2004-09-17

Applicant: Daniel Toet ,  Thomas Sigmon

Inventor： Daniel Toet ,  Thomas Sigmon

IPC: H01L21/8246 ,  H01L27/22 ,  H01L29/861 ,  H01L29/04

CPC classification number: H01L27/224 ,  B82Y10/00 ,  H01L29/861 ,  Y10S438/979

Abstract: A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.