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公开(公告)号：US06201731B1
公开(公告)日：2001-03-13
申请号：US09322490
申请日：1999-05-28
IPC分类号： C11C1604
CPC分类号： G11C11/22
摘要： A ferroelectric destructive read-out memory system includes a power source, a memory array including a memory cell, and a logic circuit for applying a signal to the memory array. Whenever a low power condition is detected in said power source, a disturb prevent circuit prevents unintended voltages due to the low power condition from disturbing the memory cell. The disturb prevent circuit also stops the operation of the logic circuit for a time sufficient to permit a rewrite cycle to be completed, thereby preventing loss of the data being rewritten.
摘要翻译： 铁电破坏性读出存储器系统包括电源，包括存储单元的存储器阵列和用于向存储器阵列施加信号的逻辑电路。 每当在所述电源中检测到低功率状况时，干扰防止电路可以防止由于低功率状况引起的非预期电压扰乱存储单元。 干扰防止电路也会使逻辑电路的操作停止足以允许完成重写周期的时间，从而防止数据被重写的损失。
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公开(公告)号：US06031754A
公开(公告)日：2000-02-29
申请号：US184474
申请日：1998-11-02
CPC分类号： G11C11/22
摘要： A ferroelectric integrated circuit memory includes a memory cell having a ferroelectric capacitor, one electrode of which is connected to a bit line through a transistor, and the other electrode of which is connected to a plate line. The bit line is also connected to system ground through a precharge transistor. In a read cycle, the precharge transistor remains on after the word line goes high connecting the capacitor to the bit line. At least a portion of the linear displacement current that flows to the bit line is drained off to ground via the precharge transistor, thereby increasing the switching voltage across the ferroelectric capacitor. The precharge transistor is turned off before or during the switching of the ferroelectric capacitor. The signal applied to the gate of the precharge transistor is boosted above the supply voltage of the memory to shorten the cycle time.
摘要翻译： 铁电集成电路存储器包括具有铁电电容器的存储单元，其一个电极通过晶体管连接到位线，并且另一个电极连接到板线。 位线也通过预充电晶体管连接到系统地。 在读周期中，在字线连接电容器到位线之后，预充电晶体管保持导通。 流过位线的线性位移电流的至少一部分经由预充电晶体管被排出到地，从而增加了铁电电容器两端的开关电压。 预充电晶体管在铁电电容器的切换之前或期间被关断。 施加到预充电晶体管的栅极的信号被提升到高于存储器的电源电压以缩短周期时间。
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公开(公告)号：US06658608B1
公开(公告)日：2003-12-02
申请号：US09400210
申请日：1999-09-21
申请人： David A. Kamp , Gary F. Derbenwick
发明人： David A. Kamp , Gary F. Derbenwick
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G11C11/22 , G11C29/50
摘要： A ferroelectric integrated circuit memory device includes: a plurality of memory cells, each including a ferroelectric material, a plurality of conducting lines, each connected to or connectable to a selected one of the memory cells; a drive circuit for applying a predetermined voltage for a predetermined time to a selected one of the conducting lines, the predetermined voltage and time being the normal voltage and time required to perform write or read functions to the memory cell, a function selected from the group of: writing a logic state to the selected memory cell, and reading the selected memory cell; and a mode control circuit responsive to an external signal for adjusting the predetermined voltage or the predetermined time to perform an operation selected from the group consisting of: a partial read of the selected memory cell, and a partial write of the selected memory cell; and applying ferroelectric stress to the memory cell. A known logic state is written to the memory cells, the cells are heated, and then read to provide output data indicative of the likelihood of premature failure for each of the memory cells. Ferroelectric stress is applied to the cells either before or after the cells are written to by repeatedly applying a voltage to the cells corresponding to a logic state opposite that of the written logic state.
摘要翻译： 铁电集成电路存储器件包括：多个存储单元，每个存储单元包括铁电材料，多个导线，每个导体线连接到或连接到选定的一个存储单元; 驱动电路，用于将预定电压预定时间施加到所选择的导线中，所述预定电压和时间是对所述存储单元执行写或读功能所需的正常电压和时间，从所述组中选择的功能 将逻辑状态写入所选存储单元，并读取所选存储单元; 以及模式控制电路，其响应于外部信号用于调整所述预定电压或所述预定时间以执行从由以下组成的组中选择的操作：所选择的存储器单元的部分读取和所选存储单元的部分写入; 并向存储单元施加铁电应力。 将已知的逻辑状态写入存储器单元，单元被加热，然后读取以提供指示每个存储器单元的过早故障的可能性的输出数据。 通过对与逻辑状态相反的逻辑状态相对应的单元反复施加电压，在单元被写入之前或之后对电池施加铁电应力。
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4.发明授权公开(公告)号：US06178138B1
公开(公告)日：2001-01-23
申请号：US09400212
申请日：1999-09-21
IPC分类号： G11C800
摘要： A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.
摘要翻译： 定时电路产生时钟信号。 地址缓冲电路相对于时钟信号异步地接收并存储第一锁存器中的第一地址和第二锁存器中的第二地址。 与存储器单元阵列相关联的存储器控制电路在第一计时的访问周期中访问对应于第一地址的阵列中的第一存储器单元，并且以第二时钟控制存取器访问对应于第二地址的阵列中的第二存储器单元 周期。 如果在所述第二访问周期之前异步地接收另一地址，则另外的地址替换第二锁存器中的第二地址。
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公开(公告)号：US07109934B2
公开(公告)日：2006-09-19
申请号：US10879379
申请日：2004-06-29
CPC分类号： G06K19/0775 , G06K19/0701 , G06K19/0715 , G06K19/0723 , G06K19/07749
摘要： A rectifier generates a rectified output and a dc power output. The rectifier has an antenna element, a tuning capacitor, a coupling capacitor, first and second rectifying diodes, and a storage capacitor. The antenna element and the tuning capacitor are coupled in parallel and grounded at one terminal. The first rectifying diode is grounded at its anode terminal and the storage capacitor is grounded at one terminal. The coupling capacitor is coupled between the ungrounded terminal of the antenna element and the cathode terminal of the first rectifying diode. The anode terminal of the second rectifying diode is coupled to the cathode terminal of the first rectifying diode. The cathode terminal of the second rectifying diode is coupled to the ungrounded terminal of the storage capacitor. The rectified output is generated between the rectifying diodes. The dc power output is generated between the second rectifying diode and the storage capacitor.
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公开(公告)号：US07053433B1
公开(公告)日：2006-05-30
申请号：US10135488
申请日：2002-04-29
申请人： Gary F. Derbenwick
发明人： Gary F. Derbenwick
IPC分类号： H01L27/108
CPC分类号： H01L27/1159 , H01L27/11502 , H01L27/11585
摘要： A ferroelectric layer within an array of ferroelectric FETs is encapsulated between a bottom barrier dielectric layer and a top barrier dielectric layer extending beyond the ferroelectric layer. The ferroelectric FETs are formed on first conductivity type silicon, each having two second conductivity type silicon regions within the first conductivity type silicon separated by some distance. The two second conductivity type silicon regions forming a source and a drain with a channel region therebetween. A silicon dioxide layer is formed on the channel region, a bottom barrier dielectric layer is formed on the silicon dioxide layer, a ferroelectric layer is formed on the bottom barrier dielectric layer, a top barrier dielectric layer is formed on the ferroelectric layer, and an electrode layer is formed on the ferroelectric layer.
摘要翻译： 铁电FET阵列内的铁电层被封装在底部阻挡介电层和延伸超出铁电层的顶部阻挡介电层之间。 铁电FET形成在第一导电型硅上，每个第一导电类型的硅在第一导电类型硅内部具有两个第二导电类型的硅区域，分隔一定距离。 两个第二导电类型的硅区域形成在其间具有沟道区域的源极和漏极。 在沟道区上形成二氧化硅层，在二氧化硅层上形成底部阻挡介电层，在底部阻挡介电层上形成铁电体层，在铁电体层上形成顶部阻挡介电层， 在铁电体层上形成电极层。
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7.发明授权Method of fabricating self-aligned MOS devices and independently formed gate dielectrics and insulating layers 失效制造自对准MOS器件和独立形成的栅极电介质和绝缘层的方法
公开(公告)号：US4397077A
公开(公告)日：1983-08-09
申请号：US331475
申请日：1981-12-16
IPC分类号： H01L27/04 , H01L21/28 , H01L21/336 , H01L21/339 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L29/78 , H01L21/76
CPC分类号： H01L27/10844 , H01L21/28273 , H01L29/66833 , H01L29/66954 , Y10S438/981
摘要： A method is described for fabricating MOS devices of the type found in very large scale integrated circuits. According to the method described herein, various gate oxides and insulating layers are fabricated independently of each other in order to independently tailor their thicknesses and thereby provide improved isolation between gate electrodes and interconnects, and independently controllable operating characteristics for multiple gate electrode structures. The fabrication of a dynamic RAM memory cell, an overlapping gate CCD device and a self-aligned MNOS transistor cell are described using the disclosed method.
摘要翻译： 描述了一种用于制造在大规模集成电路中发现的类型的MOS器件的方法。 根据本文描述的方法，各个栅极氧化物和绝缘层彼此独立地制造，以便独立地定制其厚度，从而提供栅电极和互连之间的改进的隔离，以及多个栅电极结构独立可控的工作特性。 使用所公开的方法描述了动态RAM存储器单元，重叠栅极CCD器件和自对准MNOS晶体管单元的制造。
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公开(公告)号：US06777829B2
公开(公告)日：2004-08-17
申请号：US10097846
申请日：2002-03-13
IPC分类号： H02J900
CPC分类号： G06K19/0775 , G06K19/0701 , G06K19/0715 , G06K19/0723 , G06K19/07749
摘要： A rectifier generates a rectified output and a dc power output. The rectifier has an antenna element, a tuning capacitor, a coupling capacitor, first and second rectifying diodes, and a storage capacitor. The antenna element and the tuning capacitor are coupled in parallel and grounded at one terminal. The first rectifying diode is grounded at its anode terminal and the storage capacitor is grounded at one terminal. The coupling capacitor is coupled between the ungrounded terminal of the antenna element and the cathode terminal of the first rectifying diode. The anode terminal of the second rectifying diode is coupled to the cathode terminal of the first rectifying diode. The cathode terminal of the second rectifying diode is coupled to the ungrounded terminal of the storage capacitor. The rectified output is generated between the rectifying diodes. The dc power output is generated between the second rectifying diode and the storage capacitor.
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公开(公告)号：US4486943A
公开(公告)日：1984-12-11
申请号：US588000
申请日：1984-03-12
申请人： William D. Ryden , Matthew V. Hanson , Gary F. Derbenwick , Alfred P. Gnadinger , James R. Adams
发明人： William D. Ryden , Matthew V. Hanson , Gary F. Derbenwick , Alfred P. Gnadinger , James R. Adams
IPC分类号： H01L21/265 , H01L21/28 , H01L29/08 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/265 , H01L21/28 , H01L29/78
摘要： The invented technique permits the gate length to equal the channel length: source/drain regions are self-aligned and non-overlapping with respect to their gate electrode. The non-overlapping feature, along with other optimized device characteristics, are generally provided by defining a gate electrode over a substrate, forming an implant mask of dielectric, for example, on the sides of the gate electrode, and implanting a source/drain region such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode and the implanted regions. The source/drain region is then heat driven until its side edge is substantially aligned with the edge of the gate electrode. Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and interconnects.
摘要翻译： 本发明的技术允许栅极长度等于沟道长度：源极/漏极区域相对于它们的栅极电极是自对准的且不重叠的。 通常通过在衬底上限定栅电极来形成非重叠特征以及其它优化的器件特性，例如在栅电极的侧面上形成电介质的注入掩模，以及注入源/漏区 使得植入掩模屏蔽衬底的一部分以免植入以在栅电极的侧边缘和植入区域之间提供间隙。 源极/漏极区域然后被热驱动，直到其侧边缘基本上与栅电极的边缘对准。 还使用注入掩模提供自对准的源极/漏极触点，以将栅电极与触点和互连隔离。
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公开(公告)号：US06900536B1
公开(公告)日：2005-05-31
申请号：US10132939
申请日：2002-04-26
IPC分类号： G06K19/077 , H01L20060101 , H01L21/44 , H01L23/34 , H01L23/498 , H05K1/18 , H05K5/00
CPC分类号： H05K1/186 , G06K19/07749 , H01L23/49833 , H01L2224/16 , H05K1/189 , H05K2201/055
摘要： An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.
摘要翻译： 通过在衬底上形成和图案化导电层形成电路，在另一个衬底上形成和构图导电层，在导电层之一的至少一部分上沉积介电层，将集成电路（IC）安装在 衬底，将IC耦合到导电层，以及将衬底与导电层粘合在衬底之间。 这些是单独的基底或单一基底。 IC安装在基板，导电层或电介质层上。 IC直接地或通过形成在电介质层中的开口耦合到导电层。 内部导电层可以用于将IC耦合到导电层。
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