公开(公告)号：US07091892B2

公开(公告)日：2006-08-15

申请号：US11008367

申请日：2004-12-09

申请人： David Tester ,  Gary Hague ,  Jorg Medwed

发明人： David Tester ,  Gary Hague ,  Jorg Medwed

IPC分类号： H03M1/00

CPC分类号： G05F3/262

摘要： An accurate high current mirror circuit produces a mirrored current that matches an input current to produce an accuracy at the output of a subsequent stage of amplification of greater than 0.01%. A plurality of transistor devices are arranged in a symmetrical configuration and divided into two groups. The transistors in each of the two groups are connected in parallel to produce a high mirror current from a high input current. A distribution of a source voltage produces the same source voltage at each of the plurality of transistors. An input current metallization and a mirror current metallization are formed within the symmetrical configuration to have a same value of impedance. A plurality of P-channel transistors within the current mirror circuit control a voltage of a point on the input metallization to be the same as a reference voltage, thus causing the mirror current to be referenced around the reference voltage.

摘要翻译： 精确的大电流镜电路产生与输入电流匹配的镜像电流，以在后续放大级的输出处产生大于0.01％的精度。 多个晶体管器件被布置成对称配置并分成两组。 两组中的每一个中的晶体管并联连接以从高输入电流产生高反射镜电流。 源极电压的分布在多个晶体管的每一个处产生相同的源极电压。 在对称构造内形成输入电流金属化和反射镜电流金属化以具有相同的阻抗值。 电流镜电路内的多个P沟道晶体管将输入金属化点上的电压控制为与参考电压相同，从而使反射镜电流围绕参考电压进行参考。

公开(公告)号：US07539680B2

公开(公告)日：2009-05-26

申请号：US10143155

申请日：2002-05-10

申请人： David Tester

发明人： David Tester

IPC分类号： G06F17/30

CPC分类号： G06F17/30943 ,  G06F21/6227 ,  Y10S707/99939 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99944 ,  Y10S707/99945 ,  Y10S707/99953

摘要： The invention relates to a method of controlling access to a database of a design. The method may comprise the step of identifying a version of the design by a first identifier, allocating first authorization information to the first identifier, and controlling access to the database. The first authorization information may indicate a permission of one or more users to access information in the database in respect of the first identifier. The access may be controlled in accordance with the first authorization information.

摘要翻译： 本发明涉及一种控制对设计数据库的访问的方法。 该方法可以包括通过第一标识符来识别设计的版本的步骤，将第一授权信息分配给第一标识符，以及控制对数据库的访问。 第一授权信息可以指示一个或多个用户访问关于第一标识符的数据库中的信息的许可。 可以根据第一授权信息来控制访问。

公开(公告)号：US07062695B2

公开(公告)日：2006-06-13

申请号：US10444891

申请日：2003-05-23

申请人： David Tester

发明人： David Tester

IPC分类号： G01R31/28

CPC分类号： G11C29/76 ,  G11C29/808

摘要： The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.

摘要翻译： 本发明可以提供通常具有多个可寻址存储单元和访问控制电路的电路。 访问控制电路可以被配置为拦截对多个可寻址存储器单元中的故障单元的访问。 访问控制电路还可以被配置为将访问重定向到多个可寻址存储器单元的备用单元。

公开(公告)号：US20060119496A1

公开(公告)日：2006-06-08

申请号：US11008367

申请日：2004-12-09

申请人： David Tester ,  Gary Hague ,  Jorg Medwed

发明人： David Tester ,  Gary Hague ,  Jorg Medwed

IPC分类号： H03M1/66

CPC分类号： G05F3/262

摘要： An accurate high current mirror circuit produces a mirrored current that matches an input current to produce an accuracy at the output of a subsequent stage of amplification of greater than 0.01%. A plurality of transistor devices are arranged in a symmetrical configuration and divided into two groups. The transistors in each of the two groups are connected in parallel to produce a high mirror current from a high input current. A distribution of a source voltage produces the same source voltage at each of the plurality of transistors. An input current metallization and a mirror current metallization are formed within the symmetrical configuration to have a same value of impedance. A plurality of P-channel transistors within the current mirror circuit control a voltage of a point on the input metallization to be the same as a reference voltage thus causing the mirror current to be referenced around the reference voltage.

摘要翻译： 精确的大电流镜电路产生与输入电流匹配的镜像电流，以在后续放大级的输出处产生大于0.01％的精度。 多个晶体管器件被布置成对称配置并分成两组。 两组中的每一个中的晶体管并联连接以从高输入电流产生高反射镜电流。 源极电压的分布在多个晶体管的每一个处产生相同的源极电压。 在对称构造内形成输入电流金属化和反射镜电流金属化以具有相同的阻抗值。 电流镜电路内的多个P沟道晶体管将输入金属化处的点的电压控制为与参考电压相同，从而导致镜电流围绕参考电压参考。

公开(公告)号：US06741670B2

公开(公告)日：2004-05-25

申请号：US10134740

申请日：2002-04-29

申请人： David Tester

发明人： David Tester

IPC分类号： H03K2138

CPC分类号： H03K23/58 ,  H03K21/38

摘要： A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

摘要翻译： 计数器级通常包括触发器和复位电路。 触发器可以被配置为响应于施加到时钟输入的计数信号而在第一和第二状态之间切换触发器信号以实现计数操作。 复位电路可以被配置为在不改变触发器信号的状态的情况下将计数器级复位到预定状态。

公开(公告)号：US07899659B2

公开(公告)日：2011-03-01

申请号：US10452260

申请日：2003-06-02

申请人： David Tester

发明人： David Tester

IPC分类号： G06F17/50

CPC分类号： G06T11/00 ,  G06F17/5022

摘要： A method for generating a compressed representation of a simulated waveform is disclosed. The method may have the steps of: (a) processing circuit model information, (b) identifying a segment of stable repetition; and (c) generating the compressed representation. Step (a) may generate waveform information representing a simulated waveform occurring in the circuit model. Step (b) may identify the segment in the waveform information. In step (c), the compressed waveform information may define the segment by (i) cycle information representing the waveform cycle and (ii) repetition information representing the stable repetitions of the waveform cycle to form the segment.

摘要翻译： 公开了一种用于产生模拟波形的压缩表示的方法。 该方法可以具有以下步骤：（a）处理电路模型信息，（b）识别稳定重复的段; 和（c）生成压缩表示。 步骤（a）可以产生表示电路模型中出现的模拟波形的波形信息。 步骤（b）可以识别波形信息中的段。 在步骤（c）中，压缩波形信息可以通过（i）表示波形周期的周期信息和（ii）表示波形周期的稳定重复的重复信息来形成该段来定义该段。

公开(公告)号：US06683551B1

公开(公告)日：2004-01-27

申请号：US10219638

申请日：2002-08-15

申请人： David Tester ,  Timothy Wilson

发明人： David Tester ,  Timothy Wilson

IPC分类号： H03M166

CPC分类号： H03M1/0863 ,  H03M1/742

摘要： The invention may relate to a digital to analog converter. The digital to analog converter may comprise a plurality of controllable current sources and a control circuit. The plurality of controllable current sources may include a first and a second controllable current source. Each of the plurality of controllable current sources may be controllable between a first state and a second state. The control circuit may be coupled to the plurality of controllable current sources. The control circuit may be configured to control digital to analog conversion at a sampling interval. The control circuit may be configured to control a first state transition of the first controllable current source at a timing in the sampling interval different from a second state transition of the second controllable current source.

摘要翻译： 本发明可涉及数模转换器。 数模转换器可以包括多个可控电流源和控制电路。 多个可控电流源可以包括第一和第二可控电流源。 多个可控电流源中的每一个可以在第一状态和第二状态之间是可控的。 控制电路可以耦合到多个可控电流源。 控制电路可以被配置为以采样间隔来控制数模转换。 控制电路可以被配置为在与第二可控电流源的第二状态转换不同的采样间隔的定时处控制第一可控电流源的第一状态转变。

公开(公告)号：US06650266B1

公开(公告)日：2003-11-18

申请号：US10234014

申请日：2002-09-03

申请人： David Tester

发明人： David Tester

IPC分类号： H03M166

CPC分类号： H03M1/108 ,  H03M1/682 ,  H03M1/747

摘要： The present invention may relate to a digital to analog converter for converting a digital signal to an analog signal. The digital to analog converter may comprise decoder logic, an array of clocked sub-circuits, a clock generator and a clock signal controller. The decoder logic may be configured to decode the digital signal to a plurality of control signals for controlling generation of the analog signal. The array of clocked sub-circuits may be configured to receive the control signals. The clock generator may be configured to generate a clock signal for clocking the sub-circuits. The clock signal controller may be configured to inhibit application of the clock signal to one or more of the sub-circuits.

摘要翻译： 本发明可以涉及用于将数字信号转换为模拟信号的数模转换器。 数模转换器可以包括解码器逻辑，时钟子电路阵列，时钟发生器和时钟信号控制器。 解码器逻辑可以被配置为将数字信号解码为多个控制信号，以控制模拟信号的产生。 时钟子电路的阵列可以被配置为接收控制信号。 时钟发生器可以被配置为产生用于对子电路计时的时钟信号。 时钟信号控制器可以被配置为禁止将时钟信号施加到一个或多个子电路。