公开(公告)号：US20240313795A1

公开(公告)日：2024-09-19

申请号：US18591468

申请日：2024-02-29

Applicant: Tektronix, Inc.

Inventor： Kan Tan

IPC: H03M1/10

CPC classification number: H03M1/108 ,  H03M1/1014 ,  H03M1/1085

Abstract: A test and measurement instrument includes one or more channels to receive a signal under test, each channel comprising an input port, a filter, and a sampler, at least one analog-to-digital converter (ADC), the at least one ADC having two pipes connected to the sampler of one of the one or more channels, the at least one ADC to produce digital samples of the signal at a sample rate, and one or more processors configured to execute code that causes the one more processors to acquire a spectrum of the digital samples for each pipe in the at least one ADC, and use the spectrums of the digital samples for each pipe in the at least one ADC to reconstruct the spectrum of the signal under test. A method of operating a test and measurement instrument, and a method a method of calibrating a test and measurement instrument is included.

公开(公告)号：US08203474B2

公开(公告)日：2012-06-19

申请号：US12935387

申请日：2009-03-03

Applicant: Shinichi Ogita ,  Akira Kawabe ,  Takayasu Kito

Inventor： Shinichi Ogita ,  Akira Kawabe ,  Takayasu Kito

IPC: H03M1/10

CPC classification number: H03M1/108 ,  H03M1/167 ,  H03M1/44

Abstract: In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (7, 8) based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (9). A test can be performed by supplying a test signal in place of the input analog signal. A control portion (14a) performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal. A test signal can be input with a small-scale configuration, without providing a test signal line separately from a line used for normal operation.

Abstract translation: 在每个级中，从输入的模拟信号产生与一部分位对应的数字信号，基于数字信号由DA转换部分（7,8）产生模拟参考信号，并且在输入端产生余数运算 模拟信号由余数运算部（9）进行。 可以通过提供测试信号代替输入的模拟信号来进行测试。 控制部（14a）在测试模式下进行控制，停止将输入的模拟信号提供给余数运算部，并基于数字信号停止DA转换部的基准电压选择，同时进行基于参考电压的选择 在用于测试的DA转换控制信号上，从而为剩余操作部分提供由预定的参考电压组成的测试信号，代替输入的模拟信号和模拟参考信号。 可以以小规模配置输入测试信号，而不将测试信号线与用于正常操作的线分开。

公开(公告)号：US20110025536A1

公开(公告)日：2011-02-03

申请号：US12935387

申请日：2009-03-03

Applicant: Shinichi Ogita ,  Akira Kawabe ,  Takayasu Kito

Inventor： Shinichi Ogita ,  Akira Kawabe ,  Takayasu Kito

IPC: H03M1/10

CPC classification number: H03M1/108 ,  H03M1/167 ,  H03M1/44

Abstract: In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (7, 8) based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (9). A test can be performed by supplying a test signal in place of the input analog signal. A control portion (14a) performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal. A test signal can be input with a small-scale configuration, without providing a test signal line separately from a line used for normal operation.

Abstract translation: 在每个级中，从输入的模拟信号产生与一部分位对应的数字信号，基于数字信号由DA转换部分（7,8）产生模拟参考信号，并且在输入端产生余数运算 模拟信号由余数运算部（9）进行。 可以通过提供测试信号代替输入的模拟信号来进行测试。 控制部（14a）在测试模式下进行控制，停止将输入的模拟信号提供给余数运算部，并基于数字信号停止DA转换部的基准电压选择，同时进行基于参考电压的选择 在用于测试的DA转换控制信号上，从而为剩余操作部分提供由预定的参考电压组成的测试信号，代替输入的模拟信号和模拟参考信号。 可以以小规模配置输入测试信号，而不将测试信号线与用于正常操作的线分开。

公开(公告)号：US20100182299A1

公开(公告)日：2010-07-22

申请号：US12591864

申请日：2009-12-03

Applicant: Kenji Hyoudou ,  Takashi Ichirizuka ,  Takuya Kimoto ,  Minoru Togo

Inventor： Kenji Hyoudou ,  Takashi Ichirizuka ,  Takuya Kimoto ,  Minoru Togo

IPC: G01R31/00 ,  G06F3/038

CPC classification number: H03M1/108 ,  G09G3/006 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2330/12 ,  H03M1/109 ,  H03M1/662

Abstract: A semiconductor integrated circuit is disclosed which includes: a first D/A converter; a second D/A converter; an amplifier configured to amplify an output of the first D/A converter; an operational amplifier configured to input an output of the second D/A converter; and a selector configured to effect switchover between a normal mode and a test mode, the normal mode being a mode in which the operational amplifier is caused to function as an amplifier for amplifying the output of the second D/A converter, the test mode being a mode in which the operational amplifier is caused to function as a comparator for comparing the output of the second D/A converter with the output of the first D/A converter.

Abstract translation: 公开了一种半导体集成电路，其包括：第一D / A转换器; 第二个D / A转换器; 放大器，被配置为放大所述第一D / A转换器的输出; 运算放大器，被配置为输入所述第二D / A转换器的输出; 以及选择器，其被配置为在正常模式和测试模式之间进行切换，所述正常模式是将所述运算放大器用作用于放大所述第二D / A转换器的输出的放大器的模式，所述测试模式为 导致运算放大器用作用于将第二D / A转换器的输出与第一D / A转换器的输出进行比较的比较器的模式。

公开(公告)号：US20080007440A1

公开(公告)日：2008-01-10

申请号：US11808623

申请日：2007-06-12

Applicant: Masaya Hirose ,  Kinya Daio ,  Tetsuya Oosaka ,  Tomoko Nobekawa

Inventor： Masaya Hirose ,  Kinya Daio ,  Tetsuya Oosaka ,  Tomoko Nobekawa

IPC: H03M1/10

CPC classification number: H03M1/108 ,  H03M1/0634 ,  H03M1/109

Abstract: The semiconductor device of the present invention includes: an A/D conversion circuit for A/D-converting an analog input signal and outputting a resultant conversion result; and a computation circuit for performing, in synchronization with the A/D conversion circuit, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result.

Abstract translation: 本发明的半导体器件包括：A / D转换电路，用于对模拟输入信号进行A / D转换并输出所得到的转换结果; 以及计算电路，用于与A / D转换电路同步地执行更新的转换结果的计算，而不是每当A / D转换电路的转换结果被更新时存储更新的转换结果，从而确定一个计算结果 来自A / D转换电路的多个转换结果并输出计算结果。

公开(公告)号：US20050162293A1

公开(公告)日：2005-07-28

申请号：US10512476

申请日：2002-05-13

Applicant: Helmut Theiler

Inventor： Helmut Theiler

IPC: H03M1/10 ,  H03M1/66

CPC classification number: H03M1/108 ,  H03M1/66

Abstract: In a digital-to-analog converter including an integrated test circuit, a digital input and an analog output, a comparator (5) capable of being connected with the analog output (4) and including a connection (7) for a reference voltage source, a digital test connection (11) and a logic element is provided, the logic element being connected with the test connection (11) for emitting the digital value 0 or 1 as a function of the difference between the voltage at the analog output (4) and the reference voltage.

Abstract translation: 在包括集成测试电路，数字输入和模拟输出的数模转换器中，能够与模拟输出（4）连接并包括用于参考电压源的连接（7）的比较器（5） 提供数字测试连接（11）和逻辑元件，所述逻辑元件与所述测试连接（11）连接，用于作为所述模拟输出（4）的电压之间的差值的函数发射数字值0或1 ）和参考电压。

公开(公告)号：US20040051657A1

公开(公告)日：2004-03-18

申请号：US10466706

申请日：2003-07-17

Inventor： Bengt Erik Jonsson ,  Christer Alf Jansson

IPC: H03M001/38 ,  H03M001/66 ,  H03M001/12

CPC classification number: H03M1/066 ,  H03M1/108 ,  H03M1/167 ,  H03M3/464

Abstract: An A/D converter stage including an A/D sub-converter connected to a D/A sub-converter (12) provides dynamic element matching. This is accomplished by forcing (24) the comparators (COMP1-COMP7) of the A/D sub-converter to generate a scrambled thermometer code.

Abstract translation: 包括连接到D / A子转换器（12）的A / D子转换器的A / D转换器级提供动态元件匹配。 这是通过强制（24）A / D子转换器的比较器（COMP1-COMP7）来产生加扰温度计代码来实现的。

公开(公告)号：US06650266B1

公开(公告)日：2003-11-18

申请号：US10234014

申请日：2002-09-03

Applicant: David Tester

Inventor： David Tester

IPC: H03M166

CPC classification number: H03M1/108 ,  H03M1/682 ,  H03M1/747

Abstract: The present invention may relate to a digital to analog converter for converting a digital signal to an analog signal. The digital to analog converter may comprise decoder logic, an array of clocked sub-circuits, a clock generator and a clock signal controller. The decoder logic may be configured to decode the digital signal to a plurality of control signals for controlling generation of the analog signal. The array of clocked sub-circuits may be configured to receive the control signals. The clock generator may be configured to generate a clock signal for clocking the sub-circuits. The clock signal controller may be configured to inhibit application of the clock signal to one or more of the sub-circuits.

Abstract translation: 本发明可以涉及用于将数字信号转换为模拟信号的数模转换器。 数模转换器可以包括解码器逻辑，时钟子电路阵列，时钟发生器和时钟信号控制器。 解码器逻辑可以被配置为将数字信号解码为多个控制信号，以控制模拟信号的产生。 时钟子电路的阵列可以被配置为接收控制信号。 时钟发生器可以被配置为产生用于对子电路计时的时钟信号。 时钟信号控制器可以被配置为禁止将时钟信号施加到一个或多个子电路。

公开(公告)号：US06549150B1

公开(公告)日：2003-04-15

申请号：US09682536

申请日：2001-09-17

Applicant: Raymond J. Bulaga ,  John K. Masi ,  Patrick W. Miller ,  Mark S. Styduhar ,  Donald L. Wheater

Inventor： Raymond J. Bulaga ,  John K. Masi ,  Patrick W. Miller ,  Mark S. Styduhar ,  Donald L. Wheater

IPC: H03M110

CPC classification number: H03M1/108 ,  H03M1/66

Abstract: An integrated test structure adapted to facilitate manufacturing verification of microelectronic devices such as Digital to Analog Converters (DAC) is disclosed. The test circuitry and the Circuit Under Test (CUT) are placed on an IC along with an arbitrary amount of digital logic, which drives the input of the CUT. These inputs are translated into an analog output. During a manufacturing test, this output is measured in order to determine that the IC has been manufactured correctly. The analog input of the circuit is coupled to the analog output of the DAC. The digital output of the test circuitry is coupled to the digital logic on the IC. This configuration comprises a Built In Self Test (BIST) structure. The invention allows BIST by eliminating the need to measure the analog output of the DAC external to the IC, and enables testing the CUT by using standard digital BIST techniques.

Abstract translation: 公开了一种适于促进诸如数模转换器（DAC）的微电子器件的制造验证的集成测试结构。 测试电路和被测电路（CUT）放置在IC上以及任意数量的数字逻辑，驱动CUT的输入。 这些输入被转换为模拟输出。 在制造测试期间，测量该输出以确定IC已被正确地制造。 电路的模拟输入耦合到DAC的模拟输出。 测试电路的数字输出耦合到IC上的数字逻辑。 该配置包括内置自检（BIST）结构。 本发明通过消除对IC外部DAC的模拟输出的需求而允许BIST，并且能够使用标准数字BIST技术来测试CUT。

公开(公告)号：US06297757B1

公开(公告)日：2001-10-02

申请号：US09248551

申请日：1999-02-11

Applicant: Jules D. Campbell, Jr. ,  Jiang Chen ,  Robert S. Jones, III ,  Christian Ahrens ,  Scott Willard Herrin

Inventor： Jules D. Campbell, Jr. ,  Jiang Chen ,  Robert S. Jones, III ,  Christian Ahrens ,  Scott Willard Herrin

IPC: H03M106

CPC classification number: H03M1/108 ,  H03M1/12

Abstract: A data processing system (20) includes a plurality of modules (44, 48) and an analog-to-digital converter (ADC) (46). The ADC (46) includes at least one port terminal (66) for transmitting test information from the ADC (46). The plurality of modules (44,48) and the ADC (46) are coupled to a central processing unit (CPU) (22) via an intermodule bus (42). A tester can exchange test information with the ADC (46) directly through the port terminal (66) instead of using the intermodule bus (42). Also, various sub-modules (62, 64, 60, 74) of the ADC (46) can be independently tested without performing a conversion process.

Abstract translation: 数据处理系统（20）包括多个模块（44,48）和模数转换器（ADC）（46）。 ADC（46）包括用于从ADC（46）发送测试信息的至少一个端口（66）。 多个模块（44,48）和ADC（46）经由模块间总线（42）耦合到中央处理单元（CPU）（22）。 测试人员可以直接通过端口（66）与ADC（46）交换测试信息，而不是使用模块间总线（42）。 此外，可以独立地测试ADC（46）的各个子模块（62,64,60,74），而不进行转换处理。