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公开(公告)号：US5450417A
公开(公告)日：1995-09-12
申请号：US149243
申请日：1993-10-26
CPC分类号： H03K3/356008 , H03K17/22
摘要： The power-on-reset test circuit of this invention includes two imbalanced latches to detect the occurrence of a transient power-on-reset signal. The occurrence of a transient power-on-reset signal is latched for later verification during circuit testing. Both latches are designed to default to a low voltage output (Vss) on initial power-up. One of the latches is set by the power-on-reset signal to a high-voltage output (Vcc) state. The other latch is set by a reference-potential input to a low-voltage output state. If the set latch has a high-voltage output and the other latch has a low-voltage output, then the power-on-reset circuitry is functioning properly.
摘要翻译： 本发明的上电复位测试电路包括两个不平衡锁存器，用于检测瞬态上电复位信号的发生。 瞬态上电复位信号的发生被锁存用于电路测试期间的后续验证。 两个锁存器都设计为在初始上电时默认为低电压输出（Vss）。 其中一个锁存器由上电复位信号设置为高电压输出（Vcc）状态。 另一个锁存器由参考电位输入设置为低电压输出状态。 如果设置的锁存器具有高电压输出，另一个锁存器具有低电压输出，则上电复位电路正常工作。
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公开(公告)号：US5397946A
公开(公告)日：1995-03-14
申请号：US149246
申请日：1993-10-26
CPC分类号： G11C5/143 , G11C16/225
摘要： The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for example, of two P-channel MOS transistors and one N-channel MOS transistor. The sensor circuit of this invention generates a high-voltage signal at the output if the input voltage is greater than both the reference voltage plus two P-channel threshold voltages and the supply voltage Vcc plus two P-channel threshold voltages. The power-up or power-down sequence may be in any order without adversely affecting the operation of the circuit of this invention.
摘要翻译： CMOS高电压传感器电路具有包括例如四个N沟道MOS晶体管的电压基准; 一个通道P沟道晶体管; 一个电流镜P沟道MOS晶体管; 以及包括例如两个P沟道MOS晶体管和一个N沟道MOS晶体管的常规高压传感器。 如果输入电压大于参考电压加上两个P沟道阈值电压和电源电压Vcc加上两个P沟道阈值电压，本发明的传感器电路在输出端产生高电压信号。 上电或断电顺序可以是任何顺序，而不会不利地影响本发明的电路的操作。
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3.发明授权Method and device for detecting and controlling an array source signal discharge for a memory erase operation 失效用于检测和控制用于存储器擦除操作的阵列源信号放电的方法和装置
公开(公告)号：US5424992A
公开(公告)日：1995-06-13
申请号：US112484
申请日：1993-08-25
CPC分类号： G11C16/16
摘要： An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL.sub.--). The higher voltage level bias signal (ECL.sub.--) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM.sub.--) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM.sub.--) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging. The pulse converter circuit (12) receives the array source detect signal (ASDET) and generates an erase completion signal (ERCTR) and a pulldown control signal ERCTR.sub.-- to control final discharge of the array source signals (AS) and indicate that normal memory access may resume. The pulse converter circuit (12) also generates a pulldown signal (ERD.sub.--) that controls discharge of the array source signals (AS) by preventing current surges from appearing on the array source signals (AS) during discharge.
摘要翻译： 阵列源信号放电控制器装置（10）包括接收擦除脉冲信号（ERPULSE）的脉冲转换器电路（12）。 脉冲转换器电路（12）将擦除脉冲信号（ERPULSE）转换成脉冲控制信号（ERPCL），随后将其转换为更高的电压电平偏置信号（ECL-）。 较高电压电平偏置信号（ECL-）驱动产生阵列源信号（AS）的阵列源信号发生器电路（16），以擦除由选择电路（17）确定的存储器的特定阵列子部分。 阵列源信号发生器电路（16）还产生阵列源指令信号（ASCOM-），以指示所有阵列源信号（AS）的放电状态。 擦除完成检测电路（18）监视阵列源指令信号（ASCOM-）并产生阵列源检测信号（ASDET），以指示阵列源信号（AS）放电完成。 脉冲转换器电路（12）接收阵列源检测信号（ASDET）并产生擦除完成信号（ERCTR）和下拉控制信号ERCTR-以控制阵列源信号（AS）的最终放电，并指示正常存储器存取 可能会恢复。 脉冲转换器电路（12）还通过在放电期间防止在阵列源信号（AS）上出现电流浪涌来产生控制阵列源信号（AS）的放电的下拉信号（ERD-）。
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公开(公告)号：US5396115A
公开(公告)日：1995-03-07
申请号：US149245
申请日：1993-10-26
CPC分类号： G06F1/28 , G06F1/24 , H03K17/223 , H03K5/04
摘要： The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circuit of this invention uses a static voltage reference comprised of CMOS transistors to detect the power-up condition. The circuit of this invention improves detection of a transient power-supply voltage Vcc loss and detects that power-supply voltage transient on both rising and falling edges.
摘要翻译： 本发明的上电复位电路包括电流检测电路，脉冲拉伸电路和电压参考电路。 电压基准电路例如由一个N沟道和一个P沟道MOS晶体管组成。 本发明的电路使用由CMOS晶体管组成的静态参考电压来检测上电状态。 本发明的电路改进了瞬态电源电压Vcc损耗的检测，并检测上升沿和下降沿的电源电压瞬变。
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5.发明授权Circuit and method for detecting column-line shorts in integrated-circuit memories 失效用于检测集成电路存储器中的列线短路的电路和方法
公开(公告)号：US5392248A
公开(公告)日：1995-02-21
申请号：US149242
申请日：1993-10-26
CPC分类号： G11C29/025 , G11C29/02 , G11C29/18 , G11C29/50 , G11C16/04 , G11C2029/5006
摘要： The column-line short detection circuit of this invention includes a special test circuit that turns off wordlines (15), a N-channel transistor (23) for each column line (18), a decoder (19a) that uses only the least significant column address (20d) for input to the test circuit, and a sensor (SA) to detect current between shorted column lines (18). Because the column-line short detection circuit of this invention uses only the least significant address as input for column decoder (19a), it requires a very small number of transistors.
摘要翻译： 本发明的列线短路检测电路包括一个特殊的测试电路，它关闭字线（15），用于每列列线（18）的N沟道晶体管（23），仅使用最不重要的解码器（19a） 用于输入到测试电路的列地址（20d）和用于检测短路列线（18）之间的电流的传感器（SA）。 因为本发明的列线短路检测电路仅使用最低有效地址作为列解码器（19a）的输入，所以它需要非常少数量的晶体管。
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公开(公告)号：US5120999A
公开(公告)日：1992-06-09
申请号：US652755
申请日：1991-02-08
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： Resistors are used as controlling devices to control the rate at which output buffer transistors are turned OFF and ON to control transient noise. In one form the output buffer circuit comprises a NOR circuit having a first input coupled to a data input and a second input to an enable input, a NAND circuit having a first input coupled to the data input and a second input coupled to an enable input, a first inverter transistor pair having gates coupled to the output of the NOR circuit and having source-drain paths in series coupled to a reference, a second inverter transistor pair having gates coupled to the output of the NAND circuit and having source-drain paths coupled in series to a supply, a resistor coupled between in series between the source-drain paths of the first transistor pair and the supply, a resistor coupled in series between the second transistor pair and the reference, and a third inverter transistor pair with each gate of the third transistor pair coupled to one of the outputs of the first and second inverter transistor pairs and with the output of the third transistor pair coupled to the output of the buffer circuit.
摘要翻译： 电阻器用作控制装置，用于控制输出缓冲晶体管截止和接通的速率，以控制瞬态噪声。 在一种形式中，输出缓冲电路包括NOR电路，其具有耦合到数据输入的第一输入和到使能输入的第二输入，具有耦合到数据输入的第一输入的NAND电路和耦合到使能输入的第二输入 ，具有耦合到所述NOR电路的输出并且具有串联耦合到参考的源极 - 漏极路径的栅极的第一反相器晶体管对，具有耦合到所述NAND电路的输出并具有源极 - 漏极路径的栅极的第二反相器晶体管对 串联耦合到电源，电阻器串联耦合在第一晶体管对的源极 - 漏极路径和电源之间，串联耦合在第二晶体管对和基准之间的电阻器，以及与第二晶体管对和第三晶体管对之间的第三反相器晶体管对 第三晶体管对的栅极耦合到第一和第二反相器晶体管对的输出之一以及耦合到缓冲器ci的输出的第三晶体管对的输出 rcuit
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