公开(公告)号：US5164916A

公开(公告)日：1992-11-17

申请号：US861276

申请日：1992-03-31

申请人： Andrew L. Wu ,  Derrick D. DaCosta ,  Stephen R. Coe ,  Donald C. Pierce ,  E. William Bruce, II

发明人： Andrew L. Wu ,  Derrick D. DaCosta ,  Stephen R. Coe ,  Donald C. Pierce ,  E. William Bruce, II

IPC分类号： G11C5/00 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K3/36

CPC分类号： H05K1/141 ,  H05K1/0231 ,  H05K1/0268 ,  H05K1/181 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10204 ,  H05K2203/1572 ,  H05K3/30 ,  H05K3/366

摘要： A high-density memory module has thirty-two memory integrated circuit chips, sixteen decoupling capacitors, and two resistors mounted on a double-sided multi-layer printed wiring board having a series of edge terminals for connection to a motherboard. One side of the board has a first 2.times.8 rectangular matrix of the chips, and the other side of the board has a second 2.times.8 matrix of the chips. The chips are grouped into four "strings," each of which includes eight chips which receive the same row address strobe and column address strobe. Each string is selected by a unique row address strobe. All four strings share a common data bus. Two of the strings share a first column address strobe and a first address bus, and the other two strings share a second column address strobe and a second address bus, to facilitate four-way interleaved memory access. Address, data, power, and ground terminals are distributed and dispersed along the series of edge terminals, but terminals for one address bus is disposed between a first half and a second half of the terminals for the other address bus. One of the two resistors is used for indicating the type of the memory chips in the memory module, and the other resistor is interconnected with similar resistors in other memory modules on the motherboard to provide a combined resistance indicating the number of memory modules on the motherboard.

摘要翻译： 高密度存储器模块具有32个存储器集成电路芯片，16个去耦电容器和安装在双面多层印刷电路板上的两个电阻器，其具有用于连接到母板的一系列边缘端子。 板的一侧具有芯片的第一个2x8矩形矩阵，并且板的另一侧具有芯片的第二个2x8矩阵。 这些芯片被分成四个“串”，每个“串”包括八个芯片，其接收相同的行地址选通和列地址选通。 每个字符串由唯一的行地址选通选择。 所有四个串共享一个公共数据总线。 两个串共享第一列地址选通和第一地址总线，另外两个字符串共享第二列地址选通和第二地址总线，以便于四路交错存储器访问。 地址，数据，电源和接地端子沿着一系列边缘端子分布和分散，但是用于一个地址总线的端子设置在用于另一地址总线的端子的前半部分和后半部分之间。 两个电阻器中的一个用于指示存储器模块中的存储器芯片的类型，另一个电阻器与主板上的其他存储器模块中的类似电阻器互连，以提供指示主板上的存储器模块数量的组合电阻 。