公开(公告)号：US20240007551A1

公开(公告)日：2024-01-04

申请号：US18230027

申请日：2023-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bowoong SEO ,  Hokyung Kang ,  Yongwoon Kim ,  Jonghoon Woo ,  Jinwan An

IPC: H04M1/02 ,  H05K1/02 ,  H05K1/11

CPC classification number: H04M1/0216 ,  H05K1/028 ,  H05K1/118 ,  H05K1/115 ,  H05K2201/05 ,  H05K2201/10128 ,  H05K2201/10151 ,  H05K2201/10204

Abstract: A foldable electronic device includes a display including a first and second areas; a first and second housings; a hinge structure foldably connecting the first housing and the second housing to each other on a folding axis; a flexible printed circuit board (FPCB) extending across the folding axis from a first space between the first housing and the display to a second space between the second housing and the display and including a first bending portion and a second bending portion; a sensor configured to identify an impedance in the FPCB; and a processor configured to identify a folding angle between the first housing and the second housing based on the impedance. The first bending portion includes a first sensing pattern part including a first pattern forming a first electrical path and a second pattern forming a second electrical path.

公开(公告)号：US09812387B2

公开(公告)日：2017-11-07

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/16 ,  H05K7/00 ,  H05K1/18 ,  H01L23/498 ,  H05K1/02 ,  H05K3/36 ,  H05K3/00 ,  H05K3/22 ,  H05K3/40 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

公开(公告)号：US09748023B2

公开(公告)日：2017-08-29

申请号：US14811848

申请日：2015-07-29

Applicant: GNE TECH CO., LTD.

Inventor： Jae Ku Kim

IPC: H01B17/14 ,  H05K3/42 ,  H05K3/00 ,  G02F1/1345 ,  H05K1/02 ,  H05K1/11 ,  H01B19/00 ,  H05K3/34 ,  C23F1/02 ,  C23F1/18

CPC classification number: H01B17/14 ,  B81C2203/054 ,  C23F1/02 ,  C23F1/18 ,  G02F1/13452 ,  H01B19/00 ,  H05K1/02 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/3442 ,  H05K3/42 ,  H05K2201/10204 ,  H05K2201/2036 ,  Y10T29/303 ,  Y10T29/49227 ,  Y10T428/24488 ,  Y10T428/31678

Abstract: Disclosed is a method for manufacturing a substrate gap supporter. The method includes: a first step of forming metal foils on both sides of an insulating plate; a second step of etching the metal foils to expose the insulating plate so that a plurality of stripes are arranged on both sides of the insulating plate in parallel at constant intervals, wherein the stripes expose the insulating plate at constant widths; and a third step of cutting in direction in parallel with the stripes and in direction in vertical with the stripes along one edges of the stripes to complete the gap supporter.

公开(公告)号：US20170131586A1

公开(公告)日：2017-05-11

申请号：US15318532

申请日：2015-06-19

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masaki NAKAYAMA ,  Motoji Shikota ,  Takashi Matsui ,  Yashuhiko Tanaka ,  Hiroki Miyazaki

IPC: G02F1/1345 ,  H01L23/31 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02

CPC classification number: G02F1/13452 ,  G02F1/13454 ,  H01L23/3142 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0306 ,  H05K1/181 ,  H05K3/305 ,  H05K3/323 ,  H05K2201/09781 ,  H05K2201/10136 ,  H05K2201/10204 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2924/00

Abstract: An array circuit board 11B includes a glass substrate, an IC chip 20, two ACFs 30, and a resin film 32. The IC chip 20 is disposed on the glass substrate. The ACFs 30 are disposed between the glass substrate and the IC chip 20 for electrically connecting the glass substrate and the IC chip 20 together. The ACFs 30 are separated from each other. The resin film 32 is made of resin material having cure shrinkage smaller than the ACFs 30 and disposed to fill a gap between the ACFs 30 adjacent to each other between the glass substrate and the IC chip 20.

公开(公告)号：US20170019993A1

公开(公告)日：2017-01-19

申请号：US14798384

申请日：2015-07-13

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H05K3/00 ,  H05K3/22 ,  H05K1/02 ,  H05K3/36

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

Abstract translation: 本公开涉及半导体衬底，半导体模块及其制造方法。 半导体衬底包括第一电介质结构，第二电介质结构，第一图案化导电层和第二图案化导电层。 第一电介质结构具有与第一表面相对的第一表面和第二表面。 第二电介质结构具有与第三表面相对的第三表面和第四表面，其中第四表面与第一表面相邻。 第二电介质结构限定了从第三表面延伸到第四表面的通孔。 空腔由通孔和第一电介质结构限定。 第一图案化导电层设置在第一电介质结构的第一表面上。 第二图案化导电层设置在第一介电结构的第二表面上。

公开(公告)号：US08921706B2

公开(公告)日：2014-12-30

申请号：US13823700

申请日：2010-10-01

Applicant: Mitsuaki Toda ,  Yoshio Imamura ,  Takuya Hasegawa

Inventor： Mitsuaki Toda ,  Yoshio Imamura ,  Takuya Hasegawa

IPC: H05K1/16 ,  H05K1/18 ,  H05K3/32 ,  H05K1/02

CPC classification number: H05K1/182 ,  H05K1/0269 ,  H05K1/188 ,  H05K3/32 ,  H05K2201/09918 ,  H05K2201/10204 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A component-embedded substrate includes an electrically insulating base (11) of resin, an electric or electronic embedded component (8) and a dummy embedded component (7) both embedded in the insulating base (11), a conductor pattern (18) formed on at least one side of the insulating base (11) and connected directly to or indirectly via a connection layer (6) to the embedded component (8) and the dummy embedded component (7), and a mark (10) formed on a surface of the dummy embedded component (7) and used as a reference when the conductor pattern (18) is formed, whereby positional accuracy of the conductor pattern (18) relative to the embedded component (8) can be improved.

Abstract translation: 部件嵌入式基板包括树脂电绝缘基座（11），嵌入在绝缘基座（11）中的电气或电子嵌入式部件（8）和虚拟嵌入部件（7），形成有导体图案（18） 在所述绝缘基体（11）的至少一侧上并且直接连接到所述嵌入部件（8）和所述虚拟嵌入部件（7）的连接层（6）或间接连接，以及形成在所述绝缘基体 并且当形成导体图案（18）时用作参考，从而能够提高导体图案（18）相对于嵌入部件（8）的位置精度。

公开(公告)号：US20130115428A1

公开(公告)日：2013-05-09

申请号：US13808580

申请日：2010-09-09

Applicant: Jae Ku Kim

Inventor： Jae Ku Kim

IPC: H01B17/14 ,  H01B19/00 ,  H05K1/11

CPC classification number: H01B17/14 ,  B81C2203/054 ,  C23F1/02 ,  C23F1/18 ,  G02F1/13452 ,  H01B19/00 ,  H05K1/02 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/3442 ,  H05K3/42 ,  H05K2201/10204 ,  H05K2201/2036 ,  Y10T29/303 ,  Y10T29/49227 ,  Y10T428/24488 ,  Y10T428/31678

Abstract: The substrate gap supporter (30) according to one embodiment of the present invention comprises a body (31) having a hexahedron shape and made of an insulator, metal foils (32a) and (32b) installed on opposite side surfaces of the body (31) to expose the upper portions of both side surfaces and cover the lower portions of both side surfaces, and a substrate (210) attached to the bottom surface of the body (31). According to the present invention, the gap supporter can be made through an automated process, thus precisely controlling size. Since the gap supporter is attached to the surface of the substrate, there is little possibility for a height difference to occur. And also, because the gap supporter can be installed in an automated process, it is suitable for a mass production process.

Abstract translation: 根据本发明的一个实施例的基板间隙支撑件（30）包括具有六面体形状并由绝缘体制成的主体（31），安装在主体（31）的相对侧表面上的金属箔（32a）和（32b） ）露出两侧面的上部并覆盖两个侧面的下部，以及安装在主体（31）的底面的基板（210）。 根据本发明，间隙支撑件可以通过自动化工艺制造，从而精确地控制尺寸。 由于间隙支撑体附着在基板的表面上，所以发生高度差异的可能性很小。 而且，由于间隙支架可以安装在自动化过程中，因此适用于批量生产过程。

公开(公告)号：US08395407B2

公开(公告)日：2013-03-12

申请号：US12958869

申请日：2010-12-02

Applicant: Swen Weitemeier ,  Christian Oldendorf

Inventor： Swen Weitemeier ,  Christian Oldendorf

IPC: G01R31/28

CPC classification number: G01R31/2815 ,  G01R31/2839 ,  G06F21/86 ,  H05K1/0275 ,  H05K2201/10151 ,  H05K2201/10204

Abstract: An electronic device, and associated method, provided with a circuit board (10) with a set of input contacts (IN/COM), a set of output contacts (OUT/COM) and an electrical circuit (18) connected between the input contacts (IN/COM) and the output contacts (OUT/COM), and a controller. The controller carries out a real-time test of the circuit board using a test signal introduced into the electrical circuit, the electrical circuit (18) being designed as a passive network having a characteristic transfer function and provided with at least one inductive element, which is formed by a conductor wire (201) wound into a coil around a break (202) in the circuit board (10), which in the assembled condition, is penetrated by a ferromagnetic bar or fixing pin (203), such that the inductance of the inductive element in the assembled state differs from the inductance thereof in the disassembled state.

Abstract translation: 一种具有电路板（10）的电子设备和相关方法，所述电路板具有一组输入触点（IN / COM），一组输出触点（OUT / COM）和连接在输入触点之间的电路（18） （IN / COM）和输出触点（OUT / COM）和控制器。 控制器使用引入到电路中的测试信号来执行电路板的实时测试，电路（18）被设计为具有特征传递函数并具有至少一个电感元件的无源网络，其中 由绕在电路板（10）中的断路（202）周围卷绕成线圈的导体线（201）形成，在组装状态下，该导体线被铁磁棒或固定销（203）穿透，使得电感 在组装状态下的电感元件与其分解状态下的电感不同。

公开(公告)号：US20120103674A1

公开(公告)日：2012-05-03

申请号：US12941985

申请日：2010-11-08

Applicant: MENG-CHE YU

Inventor： MENG-CHE YU

IPC: H05K1/11

CPC classification number: H05K3/4015 ,  G11C29/24 ,  H05K1/141 ,  H05K3/4046 ,  H05K2201/10204 ,  H05K2201/10409 ,  H05K2203/162

Abstract: A dummy memory card includes a circuit board and a golden finger board. The circuit board includes a first conductive element and a second conductive element connected to a first electrical load. The golden finger board extends from the circuit board and is inserted into a memory slot of a motherboard. The golden finger board includes a first power pin and a first ground pin. The first conductive element is electrically connected to the first power pin. The second conductive element is electrically connected to the second power pin.

Abstract translation: 虚拟存储卡包括电路板和金手指板。 电路板包括连接到第一电负载的第一导电元件和第二导电元件。 金手指板从电路板延伸并插入主板的存储槽中。 金指板包括第一电源引脚和第一接地引脚。 第一导电元件电连接到第一电源引脚。 第二导电元件电连接到第二电源引脚。

公开(公告)号：US08153903B2

公开(公告)日：2012-04-10

申请号：US12328955

申请日：2008-12-05

Applicant: Akihiko Kanouda ,  Ryuji Kurihara ,  Fusao Sakuramori ,  Takeshi Mochizuki ,  Yoshihiko Sugawara ,  Masami Joraku

Inventor： Akihiko Kanouda ,  Ryuji Kurihara ,  Fusao Sakuramori ,  Takeshi Mochizuki ,  Yoshihiko Sugawara ,  Masami Joraku

IPC: H05K7/20 ,  H05K7/00 ,  H05K5/00 ,  H05K1/18 ,  H05K1/03

CPC classification number: H05K7/142 ,  H05K1/0203 ,  H05K3/0061 ,  H05K3/3447 ,  H05K5/02 ,  H05K7/20963 ,  H05K2201/10204 ,  H05K2201/2036

Abstract: In a circuit board disposed in parallel to a fixing plane, a guard spacer (abutting member) is disposed on a multi-layer printed circuit board on the side of the fixing plane to suppress deformation of the multi-layer printed circuit board to prevent short circuit if an impact is applied to the circuit board. The guard spacer may be a dummy electronic component or a plate member. An image display using the circuit board is also disclosed.

Abstract translation: 在与固定平面平行设置的电路板中，在固定平面侧的多层印刷电路板上设置防护间隔物（抵接构件），以抑制多层印刷电路板的变形，防止短路 电路如果对电路板施加冲击。 防护间隔件可以是虚拟电子部件或板部件。 还公开了使用电路板的图像显示。