公开(公告)号：US5850324A

公开(公告)日：1998-12-15

申请号：US818474

申请日：1997-03-13

申请人： Andrew L. Wu ,  Warren W. Goller ,  Bruce Provencher

发明人： Andrew L. Wu ,  Warren W. Goller ,  Bruce Provencher

IPC分类号： G11B5/31 ,  G11B5/39

CPC分类号： G11B5/3906 ,  G11B5/3932 ,  G11B5/3967 ,  G11B5/3116 ,  G11B5/3133

摘要： A magnetic head 50 comprises a substrate 55 including a magnetoresistive sensor 60 having (i) a magnetoresistive element 65 with a top surface 105, and (ii) an electrically conducting portion 75. Conductor leads 70 are electrically connected to the electrically conducting portion 75 of the magnetoresistive sensor 60. First and second dielectric isolators 100, 125 electrically isolate the conductor leads. The dielectric isolators 100, 125 terminate adjacent to, and substantially without covering, the top surface of the magnetoresistive element. Preferably, the first dielectric isolators 100 comprise (i) an inner edge 115 abutting and covering the peripheral edge 110 of the magnetoresistive sensor, and (ii) an upper surface 120 substantially in the same plane as the top surface 105 of the magnetoresistive sensor. The magnetic head 50 has superior magnetic data reading accuracy and reliability.

摘要翻译： 磁头50包括衬底55，衬底55包括具有（i）具有顶表面105的磁阻元件65和（ii）导电部分75的磁致电阻传感器60，以及（ii）导电部分75.导体引线70电连接到导电部分75的导电部分75 磁阻传感器60.第一和第二介质隔离器100,125电导体隔离导体引线。 介质隔离器100,125与磁阻元件的顶表面相邻并基本上不覆盖。 优选地，第一介电隔离器100包括（i）邻接并覆盖磁阻传感器的周缘110的内边缘115，以及（ii）与磁阻传感器的顶表面105基本上在同一平面中的上表面120。 磁头50具有优异的磁数据读取精度和可靠性。

公开(公告)号：US5804085A

公开(公告)日：1998-09-08

申请号：US791401

申请日：1997-01-30

申请人： Andrew L. Wu ,  Paul Duval ,  Thomas Ferraguto

发明人： Andrew L. Wu ,  Paul Duval ,  Thomas Ferraguto

IPC分类号： G11B5/23 ,  G11B5/31 ,  G11B5/39 ,  G11B5/127

CPC分类号： G11B5/3967 ,  G11B5/3116 ,  G11B5/3163 ,  G11B5/232 ,  Y10T29/49046

摘要： A pole-trimmed writer for an MR read/write data transducer which may be produced without significant re-deposition of Al.sub.2 O.sub.3 or NiFe on the sides of the writer poles. The process disclosed herein advantageously provides an upper (top) pole which is processed to project a pair of relatively thin, laterally extending lower flanges, prior to the use of the upper pole as a mask to subsequent ion milling of the lower pole, or shared shield. In a preferred embodiment, the process for producing the flange is implemented in conjunction with the deposition of a single copper (Cu) or dual Al.sub.2 O.sub.3 and chromium (Cr) overlayers formed on the upper pole seed layer followed by the top pole formation and selective removal of a predetermined amount of the underlying portions of the gap material prior to a subsequent ion milling operation and further processing of the read/write head.

公开(公告)号：US5164916A

公开(公告)日：1992-11-17

申请号：US861276

申请日：1992-03-31

申请人： Andrew L. Wu ,  Derrick D. DaCosta ,  Stephen R. Coe ,  Donald C. Pierce ,  E. William Bruce, II

发明人： Andrew L. Wu ,  Derrick D. DaCosta ,  Stephen R. Coe ,  Donald C. Pierce ,  E. William Bruce, II

IPC分类号： G11C5/00 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K3/36

CPC分类号： H05K1/141 ,  H05K1/0231 ,  H05K1/0268 ,  H05K1/181 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10204 ,  H05K2203/1572 ,  H05K3/30 ,  H05K3/366

摘要： A high-density memory module has thirty-two memory integrated circuit chips, sixteen decoupling capacitors, and two resistors mounted on a double-sided multi-layer printed wiring board having a series of edge terminals for connection to a motherboard. One side of the board has a first 2.times.8 rectangular matrix of the chips, and the other side of the board has a second 2.times.8 matrix of the chips. The chips are grouped into four "strings," each of which includes eight chips which receive the same row address strobe and column address strobe. Each string is selected by a unique row address strobe. All four strings share a common data bus. Two of the strings share a first column address strobe and a first address bus, and the other two strings share a second column address strobe and a second address bus, to facilitate four-way interleaved memory access. Address, data, power, and ground terminals are distributed and dispersed along the series of edge terminals, but terminals for one address bus is disposed between a first half and a second half of the terminals for the other address bus. One of the two resistors is used for indicating the type of the memory chips in the memory module, and the other resistor is interconnected with similar resistors in other memory modules on the motherboard to provide a combined resistance indicating the number of memory modules on the motherboard.

摘要翻译： 高密度存储器模块具有32个存储器集成电路芯片，16个去耦电容器和安装在双面多层印刷电路板上的两个电阻器，其具有用于连接到母板的一系列边缘端子。 板的一侧具有芯片的第一个2x8矩形矩阵，并且板的另一侧具有芯片的第二个2x8矩阵。 这些芯片被分成四个“串”，每个“串”包括八个芯片，其接收相同的行地址选通和列地址选通。 每个字符串由唯一的行地址选通选择。 所有四个串共享一个公共数据总线。 两个串共享第一列地址选通和第一地址总线，另外两个字符串共享第二列地址选通和第二地址总线，以便于四路交错存储器访问。 地址，数据，电源和接地端子沿着一系列边缘端子分布和分散，但是用于一个地址总线的端子设置在用于另一地址总线的端子的前半部分和后半部分之间。 两个电阻器中的一个用于指示存储器模块中的存储器芯片的类型，另一个电阻器与主板上的其他存储器模块中的类似电阻器互连，以提供指示主板上的存储器模块数量的组合电阻 。

公开(公告)号：US4770897A

公开(公告)日：1988-09-13

申请号：US46160

申请日：1987-05-05

申请人： Andrew L. Wu

发明人： Andrew L. Wu

IPC分类号： H05K3/46 ,  H01L21/48 ,  H01L23/538 ,  H05K3/14 ,  H05K3/18 ,  B05D5/12

CPC分类号： H05K3/184 ,  H01L21/4857 ,  H05K3/143

摘要： A method for fabricating a multilayer interconnection system that is fully planar with completely sealed and corrosion resistant conductors separated by dielectric material.

公开(公告)号：US07751154B2

公开(公告)日：2010-07-06

申请号：US11133493

申请日：2005-05-19

申请人： Andrew L. Wu

发明人： Andrew L. Wu

IPC分类号： G11B5/33 ,  G11B5/147

CPC分类号： G11B5/3166 ,  G11B5/3169 ,  G11B5/3173 ,  G11B5/3903 ,  G11B5/3929 ,  G11B5/40

摘要： In one aspect described herein, a read head having one or more magnetoresistive (MR) sensors (or devices) is provided. In one example, the read head includes an MR sensor and an insulator layer disposed at the same level as the MR sensor. The read head further includes a bearing surface, wherein the insulator layer forms a portion of the bearing surface and is disposed between a surface of the MR sensor and the bearing surface to provide protection for the MR sensor from exposure to the bearing surface. The MR sensor may include a stack of thin-film layers to form an AMR, GMR, or TGMR sensor element. The stack may further include a slanted surface portion, wherein the insulator layer is disposed on the slanted surface portion, thereby recessing the MR sensor from the bearing surface.

摘要翻译： 在本文描述的一个方面，提供了具有一个或多个磁阻（MR）传感器（或设备）的读取头。 在一个示例中，读取头包括布置在与MR传感器相同水平的MR传感器和绝缘体层。 所述读取头还包括支承表面，其中所述绝缘体层形成所述支承表面的一部分并且设置在所述MR传感器的表面和所述支承表面之间，以提供所述MR传感器不受暴露于所述支承表面的保护。 MR传感器可以包括一叠薄膜层以形成AMR，GMR或TGMR传感器元件。 叠层还可包括倾斜表面部分，其中绝缘体层设置在倾斜表面部分上，从而将MR传感器从轴承表面凹入。

公开(公告)号：US07170721B2

公开(公告)日：2007-01-30

申请号：US10183329

申请日：2002-06-25

申请人： Andrew L. Wu

发明人： Andrew L. Wu

IPC分类号： G11B5/39 ,  G11B5/31

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G11B5/3133 ,  G11B5/3146 ,  G11B5/3916 ,  G11B5/40 ,  G11B5/4893 ,  G11B2005/3996

摘要： A flux guide protected magnetoresistive sensor in a tape drive read/write head is presented. The magnetoresistive sensor has a tape bearing surface, and includes a magnetoresistive sensing element and a flux guide disposed on a surface of the magnetoresistive sensing element to form a portion of the tape bearing surface.

摘要翻译： 介绍了磁带驱动读/写磁头中的磁通导向保护磁阻传感器。 磁阻传感器具有带状表面，并且包括磁阻感测元件和设置在磁阻感测元件的表面上以形成带状表面的一部分的磁通引导件。

公开(公告)号：US6141183A

公开(公告)日：2000-10-31

申请号：US115147

申请日：1998-07-14

申请人： Andrew L. Wu ,  Paul Duval ,  Thomas Ferraguto

发明人： Andrew L. Wu ,  Paul Duval ,  Thomas Ferraguto

IPC分类号： G11B5/23 ,  G11B5/31 ,  G11B5/39

CPC分类号： G11B5/3967 ,  G11B5/3116 ,  G11B5/3163 ,  G11B5/232 ,  Y10T29/49046

摘要： A pole-trimmed writer for an MR read/write data transducer which may be produced without significant re-deposition of Al.sub.2 O.sub.3 or NiFe on the sides of the writer poles. The process disclosed herein advantageously provides an upper (top) pole which is processed to project a pair of relatively thin, laterally extending lower flanges, prior to the use of the upper pole as a mask to subsequent ion milling of the lower pole, or shared shield. In a preferred embodiment, the process for producing the flange is implemented in conjunction with the deposition of a single copper (Cu) or dual Al.sub.2 O.sub.3 and chromium (Cr) overlayers formed on the upper pole seed layer followed by the top pole formation and selective removal of a predetermined amount of the underlying portions of the gap material prior to a subsequent ion milling operation and further processing of the read/write head.

摘要翻译： 用于MR读/写数据传感器的极修整写入器，其可以在写器极的侧面上不显着再沉积Al 2 O 3或NiFe的情况下产生。 本文公开的方法有利地提供了上（上）杆，其被加工成在使用上极作为掩模之前投影一对相对薄的横向延伸的下凸缘，以后续离子铣削下极，或共享 屏蔽。 在一个优选实施例中，用于制造凸缘的方法结合沉积形成在上极种子层上的单个铜（Cu）或双重Al 2 O 3和铬（Cr）覆盖层，然后进行顶极形成和选择性去除 在随后的离子铣削操作和读/写头的进一步处理之前，预定量的间隙材料的下面部分。

公开(公告)号：US4617193A

公开(公告)日：1986-10-14

申请号：US505046

申请日：1983-06-16

申请人： Andrew L. Wu

发明人： Andrew L. Wu

IPC分类号： H01L21/3205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/528 ,  B05D3/06 ,  B05D5/12 ,  B44C1/22

CPC分类号： H01L21/7684 ,  H01L21/76838 ,  H01L23/5283 ,  H01L2924/0002

摘要： An integrated circuit having a plurality of devices on a substrate is disclosed, wherein a plurality of metallization layers, separated by a plurality of insulating layers, are used to interconnect the devices. Each metallization layer is recessed in an upper portion of a corresponding dielectric layer. A metallization layer is connected to a lower one, or, in the case of the first metallization layer, to the devices, by solid contacts extending through via windows in the lower portion of the corresponding dielectric layer. A method of manufacturing such an integrated circuit is also disclosed, whereby each layer is formed in two steps. First, the lower portion of the insulating layer is deposited, the contact pattern opened and the vias windows filled with metal to provide contacts even with the top surface of the lower portion of the insulating layer. Then, the upper portion of the insulating layer is deposited over the lower portion, the metallization pattern opened, and the pattern filled with metal up to and even with the top surface of the upper portion of the insulating layer. The metal filling step is produced by depositing a metal layer over the corresponding portion of opened insulating layer, masking the opened regions and selectively and directionally removing the unprotected metal layer.

摘要翻译： 公开了一种在衬底上具有多个器件的集成电路，其中由多个绝缘层隔开的多个金属化层用于互连器件。 每个金属化层凹入相应电介质层的上部。 金属化层连接到较低的金属化层，或者在第一金属化层的情况下，通过固体触点延伸穿过相应电介质层的下部中的通孔。 还公开了一种制造这样的集成电路的方法，其中每个层分成两个步骤。 首先，沉积绝缘层的下部，接触图案打开，并且通孔窗口填充有金属以提供甚至与绝缘层的下部的顶部表面的接触。 然后，绝缘层的上部被沉积在下部，金属化图案打开，并且图案填充有金属直到甚至与绝缘层的上部的顶表面。 金属填充步骤通过在开放的绝缘层的相应部分上沉积金属层，掩蔽开放的区域并选择性地和定向地去除未保护的金属层来制造。

公开(公告)号：US5448822A

公开(公告)日：1995-09-12

申请号：US29125

申请日：1993-03-10

申请人： Andrew L. Wu ,  Paul J. Duval

发明人： Andrew L. Wu ,  Paul J. Duval

IPC分类号： G11B5/31 ,  H01F41/04 ,  G11B5/842

CPC分类号： G11B5/3163 ,  G11B5/313 ,  H01F41/042 ,  Y10T29/49062

摘要： A method of making a thin film magnetic head having multi-layer coils wherein a raised insulative photoresist spiral pattern having undercut sidewalls is formed. Two layers of coils are fabricated simultaneously by evaporating metal onto the upper surface of the spiral pattern and in spaces between the pattern. The cross-section of the bottom coil decreases in width with an increase in height. The coils are insulated from each other with a layer of insulative photoresist.

摘要翻译： 一种制造具有多层线圈的薄膜磁头的方法，其中形成具有底切侧壁的凸起的绝缘光致抗蚀剂螺旋图案。 通过将金属蒸发到螺旋图案的上表面和图案之间的空间中同时制造两层线圈。 底部线圈的横截面随着高度的增加而减小。 线圈由绝缘光致抗蚀剂层彼此绝缘。

公开(公告)号：US5331496A

公开(公告)日：1994-07-19

申请号：US837358

申请日：1992-02-14

申请人： Andrew L. Wu ,  Sharat Batra

发明人： Andrew L. Wu ,  Sharat Batra

IPC分类号： G11B5/31 ,  G11B5/147 ,  G11B5/17

CPC分类号： G11B5/3163 ,  G11B5/3113 ,  G11B5/313 ,  Y10T29/49034 ,  Y10T29/49064 ,  Y10T29/49066

摘要： A thin film magnetic head, and process for making the same, features a thin film magnetic transducer formed from multiple layers of film and having a magnetic yoke interacting with an electrical coil. The yoke has multiple magnetic flux circuits, deposited on multiple layers of film, encircling the center of the transducer and connected together by proximal and distal vias. A coil has multiple turns intertwined with the yoke, passing between the distal and proximal vias so that the distal vias are exterior to the coil and the proximal Vias are interior to the coil, to provide at least four magnetic flux interactions between the coil and the yoke. In preferred embodiments at least one layer of the film is deposited with at least two pole pieces having different easy axis orientations. In other preferred embodiments at least one distal via is configured as an elongated "flux strap" for conducting magnetic flux along the length of the via in a direction oblique to the easy axis of either pole piece coupled together by the magnetic flux strap.

摘要翻译： 一种薄膜磁头及其制造方法，其特征在于由多层薄膜形成并具有与电线圈相互作用的磁轭的薄膜磁换能器。 轭具有多个磁通电路，沉积在多层膜上，环绕换能器的中心并通过近端和远端通孔连接在一起。 线圈具有与轭相交的多个匝，在远端和近端通孔之间通过，使得远端通孔位于线圈的外部，并且近侧通道位于线圈的内部，以在线圈和线圈之间提供至少四个磁通量相互作用 轭。 在优选实施例中，至少一层膜沉积有具有不同易轴取向的至少两个极片。 在其它优选实施例中，至少一个远端通孔被配置为细长的“通量带”，用于沿着通孔的长度沿着与通过磁通带耦合在一起的任一极靴的容易轴线倾斜的方向导通磁通。