公开(公告)号：US5164916A

公开(公告)日：1992-11-17

申请号：US861276

申请日：1992-03-31

申请人： Andrew L. Wu ,  Derrick D. DaCosta ,  Stephen R. Coe ,  Donald C. Pierce ,  E. William Bruce, II

发明人： Andrew L. Wu ,  Derrick D. DaCosta ,  Stephen R. Coe ,  Donald C. Pierce ,  E. William Bruce, II

IPC分类号： G11C5/00 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K3/36

CPC分类号： H05K1/141 ,  H05K1/0231 ,  H05K1/0268 ,  H05K1/181 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10204 ,  H05K2203/1572 ,  H05K3/30 ,  H05K3/366

摘要： A high-density memory module has thirty-two memory integrated circuit chips, sixteen decoupling capacitors, and two resistors mounted on a double-sided multi-layer printed wiring board having a series of edge terminals for connection to a motherboard. One side of the board has a first 2.times.8 rectangular matrix of the chips, and the other side of the board has a second 2.times.8 matrix of the chips. The chips are grouped into four "strings," each of which includes eight chips which receive the same row address strobe and column address strobe. Each string is selected by a unique row address strobe. All four strings share a common data bus. Two of the strings share a first column address strobe and a first address bus, and the other two strings share a second column address strobe and a second address bus, to facilitate four-way interleaved memory access. Address, data, power, and ground terminals are distributed and dispersed along the series of edge terminals, but terminals for one address bus is disposed between a first half and a second half of the terminals for the other address bus. One of the two resistors is used for indicating the type of the memory chips in the memory module, and the other resistor is interconnected with similar resistors in other memory modules on the motherboard to provide a combined resistance indicating the number of memory modules on the motherboard.

摘要翻译： 高密度存储器模块具有32个存储器集成电路芯片，16个去耦电容器和安装在双面多层印刷电路板上的两个电阻器，其具有用于连接到母板的一系列边缘端子。 板的一侧具有芯片的第一个2x8矩形矩阵，并且板的另一侧具有芯片的第二个2x8矩阵。 这些芯片被分成四个“串”，每个“串”包括八个芯片，其接收相同的行地址选通和列地址选通。 每个字符串由唯一的行地址选通选择。 所有四个串共享一个公共数据总线。 两个串共享第一列地址选通和第一地址总线，另外两个字符串共享第二列地址选通和第二地址总线，以便于四路交错存储器访问。 地址，数据，电源和接地端子沿着一系列边缘端子分布和分散，但是用于一个地址总线的端子设置在用于另一地址总线的端子的前半部分和后半部分之间。 两个电阻器中的一个用于指示存储器模块中的存储器芯片的类型，另一个电阻器与主板上的其他存储器模块中的类似电阻器互连，以提供指示主板上的存储器模块数量的组合电阻 。

公开(公告)号：US5191404A

公开(公告)日：1993-03-02

申请号：US767571

申请日：1991-09-30

申请人： Andrew L. Wu ,  Donald W. Smelser ,  E. William Bruce, II ,  John O'Dea

发明人： Andrew L. Wu ,  Donald W. Smelser ,  E. William Bruce, II ,  John O'Dea

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H05K1/14 ,  H05K3/34

CPC分类号： H05K1/144 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1064 ,  H01L2225/107 ,  H05K2201/10946 ,  H05K3/3421

摘要： A low-profile, high-density package for intergrated circuit chips is provided. A first multichip memory module includes first and second interconnect members having low-profile memory chips mounted on a first side of each member. Low-profile edge clips are employed to mechanically connect a second side of the second member to a second side of the first member, and to electrically connect the first sides of the members to a first surface of a circuit board. Likewise, a second multichip memory module includes first and second interconnect members having low-profile memory chips mounted to a first side of each member. Low-profile edge clips are employed to mechanically connect the second sides of the members, and to electrically connect the first sides of the members to a second surface of the circuit board. A thermal management technique that distributes thermal loads is thereafter applied to create a high-density package capable of insertion into a standard computer backplane and cabinet.

摘要翻译： 提供了一种用于集成电路芯片的低调，高密度封装。 第一多芯片存储器模块包括具有安装在每个构件的第一侧上的薄型存储芯片的第一和第二互连构件。 使用低轮廓边缘夹将机械地将第二构件的第二侧连接到第一构件的第二侧，并且将构件的第一侧电连接到电路板的第一表面。 类似地，第二多芯片存储器模块包括第一和第二互连构件，其具有安装到每个构件的第一侧的低轮廓存储器芯片。 使用低轮廓边缘夹将机构连接构件的第二侧，并将构件的第一侧电连接到电路板的第二表面。 此后应用分配热负荷的热管理技术来产生能够插入到标准计算机背板和机柜中的高密度封装。

公开(公告)号：US5448822A

公开(公告)日：1995-09-12

申请号：US29125

申请日：1993-03-10

申请人： Andrew L. Wu ,  Paul J. Duval

发明人： Andrew L. Wu ,  Paul J. Duval

IPC分类号： G11B5/31 ,  H01F41/04 ,  G11B5/842

CPC分类号： G11B5/3163 ,  G11B5/313 ,  H01F41/042 ,  Y10T29/49062

摘要： A method of making a thin film magnetic head having multi-layer coils wherein a raised insulative photoresist spiral pattern having undercut sidewalls is formed. Two layers of coils are fabricated simultaneously by evaporating metal onto the upper surface of the spiral pattern and in spaces between the pattern. The cross-section of the bottom coil decreases in width with an increase in height. The coils are insulated from each other with a layer of insulative photoresist.

摘要翻译： 一种制造具有多层线圈的薄膜磁头的方法，其中形成具有底切侧壁的凸起的绝缘光致抗蚀剂螺旋图案。 通过将金属蒸发到螺旋图案的上表面和图案之间的空间中同时制造两层线圈。 底部线圈的横截面随着高度的增加而减小。 线圈由绝缘光致抗蚀剂层彼此绝缘。

公开(公告)号：US5331496A

公开(公告)日：1994-07-19

申请号：US837358

申请日：1992-02-14

申请人： Andrew L. Wu ,  Sharat Batra

发明人： Andrew L. Wu ,  Sharat Batra

IPC分类号： G11B5/31 ,  G11B5/147 ,  G11B5/17

CPC分类号： G11B5/3163 ,  G11B5/3113 ,  G11B5/313 ,  Y10T29/49034 ,  Y10T29/49064 ,  Y10T29/49066

摘要： A thin film magnetic head, and process for making the same, features a thin film magnetic transducer formed from multiple layers of film and having a magnetic yoke interacting with an electrical coil. The yoke has multiple magnetic flux circuits, deposited on multiple layers of film, encircling the center of the transducer and connected together by proximal and distal vias. A coil has multiple turns intertwined with the yoke, passing between the distal and proximal vias so that the distal vias are exterior to the coil and the proximal Vias are interior to the coil, to provide at least four magnetic flux interactions between the coil and the yoke. In preferred embodiments at least one layer of the film is deposited with at least two pole pieces having different easy axis orientations. In other preferred embodiments at least one distal via is configured as an elongated "flux strap" for conducting magnetic flux along the length of the via in a direction oblique to the easy axis of either pole piece coupled together by the magnetic flux strap.

摘要翻译： 一种薄膜磁头及其制造方法，其特征在于由多层薄膜形成并具有与电线圈相互作用的磁轭的薄膜磁换能器。 轭具有多个磁通电路，沉积在多层膜上，环绕换能器的中心并通过近端和远端通孔连接在一起。 线圈具有与轭相交的多个匝，在远端和近端通孔之间通过，使得远端通孔位于线圈的外部，并且近侧通道位于线圈的内部，以在线圈和线圈之间提供至少四个磁通量相互作用 轭。 在优选实施例中，至少一层膜沉积有具有不同易轴取向的至少两个极片。 在其它优选实施例中，至少一个远端通孔被配置为细长的“通量带”，用于沿着通孔的长度沿着与通过磁通带耦合在一起的任一极靴的容易轴线倾斜的方向导通磁通。

公开(公告)号：US5130768A

公开(公告)日：1992-07-14

申请号：US624034

申请日：1990-12-07

申请人： Andrew L. Wu ,  Martin W. Czekalski

发明人： Andrew L. Wu ,  Martin W. Czekalski

IPC分类号： H01L23/40 ,  H01L23/473 ,  H01L23/498 ,  H01L23/538 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC分类号： H05K1/141 ,  H01L23/4006 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/5385 ,  H01L2023/4062 ,  H01L2924/0002 ,  H05K2201/09472 ,  H05K2201/10318 ,  H05K2201/10477 ,  H05K3/3421 ,  H05K3/368

摘要： A compact high-density packaging arrangement for high-performance semiconductor devices includes a plurality of high-performance semiconductor chips connected to a multilayer daughter substrate member using a bare chip assembly technique known as bonded pin technology. Internal bonded pins are formed on bonding pads of the chips and soldered to conductive pads in solder wells located on the daughter substrate to provide a first level of interconnection for the chips. A larger, multilayer mother substrate member has a plurality of apertures formed in one surface thereof. These apertures are terminated by a top side of a metallized base layer of the substrate. An opposite surface of the mother substrate, i.e. a bottom side of the base layer, is affixed in thermal conductive relation to a metallic cold plate adapted for receiving a cooling fluid. External bonded pins are formed on bonding pads of the daughter substrate and inserted into corresponding solder wells located on the mother substrate. Concurrently, the bare chips are situated into the apertures in intimate thermal conductive relation to the cold plate via the metallized base layer. The pins are then soldered to conductive pads in the solder wells, thereby providing a second level of chip interconnection when other chip-populated daughter substrates are mounted thereon.

摘要翻译： 用于高性能半导体器件的紧凑型高密度封装装置包括使用称为接合引脚技术的裸芯片组装技术连接到多层子衬底构件的多个高性能半导体芯片。 内部接合引脚形成在芯片的焊盘上，并焊接到位于子基板上的焊料阱中的导电焊盘，以提供芯片的第一级互连级别。 较大的多层母体衬底构件在其一个表面中形成有多个孔。 这些孔由衬底的金属化基底层的顶侧终止。 母基板的相对表面，即基底层的底侧，与适于接收冷却流体的金属冷板以导热关系固定。 外部接合引脚形成在子基板的焊盘上并插入位于母基板上的相应的焊接阱中。 同时，裸芯片通过金属化基底层与冷板以紧密的导热关系位于孔中。 然后将引脚焊接到焊料阱中的导电焊盘，从而当安装其上的其它芯片填充的子基板时提供第二级芯片互连。

公开(公告)号：US5850324A

公开(公告)日：1998-12-15

申请号：US818474

申请日：1997-03-13

申请人： Andrew L. Wu ,  Warren W. Goller ,  Bruce Provencher

发明人： Andrew L. Wu ,  Warren W. Goller ,  Bruce Provencher

IPC分类号： G11B5/31 ,  G11B5/39

CPC分类号： G11B5/3906 ,  G11B5/3932 ,  G11B5/3967 ,  G11B5/3116 ,  G11B5/3133

摘要： A magnetic head 50 comprises a substrate 55 including a magnetoresistive sensor 60 having (i) a magnetoresistive element 65 with a top surface 105, and (ii) an electrically conducting portion 75. Conductor leads 70 are electrically connected to the electrically conducting portion 75 of the magnetoresistive sensor 60. First and second dielectric isolators 100, 125 electrically isolate the conductor leads. The dielectric isolators 100, 125 terminate adjacent to, and substantially without covering, the top surface of the magnetoresistive element. Preferably, the first dielectric isolators 100 comprise (i) an inner edge 115 abutting and covering the peripheral edge 110 of the magnetoresistive sensor, and (ii) an upper surface 120 substantially in the same plane as the top surface 105 of the magnetoresistive sensor. The magnetic head 50 has superior magnetic data reading accuracy and reliability.

摘要翻译： 磁头50包括衬底55，衬底55包括具有（i）具有顶表面105的磁阻元件65和（ii）导电部分75的磁致电阻传感器60，以及（ii）导电部分75.导体引线70电连接到导电部分75的导电部分75 磁阻传感器60.第一和第二介质隔离器100,125电导体隔离导体引线。 介质隔离器100,125与磁阻元件的顶表面相邻并基本上不覆盖。 优选地，第一介电隔离器100包括（i）邻接并覆盖磁阻传感器的周缘110的内边缘115，以及（ii）与磁阻传感器的顶表面105基本上在同一平面中的上表面120。 磁头50具有优异的磁数据读取精度和可靠性。

公开(公告)号：US5804085A

公开(公告)日：1998-09-08

申请号：US791401

申请日：1997-01-30

申请人： Andrew L. Wu ,  Paul Duval ,  Thomas Ferraguto

发明人： Andrew L. Wu ,  Paul Duval ,  Thomas Ferraguto

IPC分类号： G11B5/23 ,  G11B5/31 ,  G11B5/39 ,  G11B5/127

CPC分类号： G11B5/3967 ,  G11B5/3116 ,  G11B5/3163 ,  G11B5/232 ,  Y10T29/49046

摘要： A pole-trimmed writer for an MR read/write data transducer which may be produced without significant re-deposition of Al.sub.2 O.sub.3 or NiFe on the sides of the writer poles. The process disclosed herein advantageously provides an upper (top) pole which is processed to project a pair of relatively thin, laterally extending lower flanges, prior to the use of the upper pole as a mask to subsequent ion milling of the lower pole, or shared shield. In a preferred embodiment, the process for producing the flange is implemented in conjunction with the deposition of a single copper (Cu) or dual Al.sub.2 O.sub.3 and chromium (Cr) overlayers formed on the upper pole seed layer followed by the top pole formation and selective removal of a predetermined amount of the underlying portions of the gap material prior to a subsequent ion milling operation and further processing of the read/write head.

公开(公告)号：US4770897A

公开(公告)日：1988-09-13

申请号：US46160

申请日：1987-05-05

申请人： Andrew L. Wu

发明人： Andrew L. Wu

IPC分类号： H05K3/46 ,  H01L21/48 ,  H01L23/538 ,  H05K3/14 ,  H05K3/18 ,  B05D5/12

CPC分类号： H05K3/184 ,  H01L21/4857 ,  H05K3/143

摘要： A method for fabricating a multilayer interconnection system that is fully planar with completely sealed and corrosion resistant conductors separated by dielectric material.

公开(公告)号：US07751154B2

公开(公告)日：2010-07-06

申请号：US11133493

申请日：2005-05-19

申请人： Andrew L. Wu

发明人： Andrew L. Wu

IPC分类号： G11B5/33 ,  G11B5/147

CPC分类号： G11B5/3166 ,  G11B5/3169 ,  G11B5/3173 ,  G11B5/3903 ,  G11B5/3929 ,  G11B5/40

摘要： In one aspect described herein, a read head having one or more magnetoresistive (MR) sensors (or devices) is provided. In one example, the read head includes an MR sensor and an insulator layer disposed at the same level as the MR sensor. The read head further includes a bearing surface, wherein the insulator layer forms a portion of the bearing surface and is disposed between a surface of the MR sensor and the bearing surface to provide protection for the MR sensor from exposure to the bearing surface. The MR sensor may include a stack of thin-film layers to form an AMR, GMR, or TGMR sensor element. The stack may further include a slanted surface portion, wherein the insulator layer is disposed on the slanted surface portion, thereby recessing the MR sensor from the bearing surface.

摘要翻译： 在本文描述的一个方面，提供了具有一个或多个磁阻（MR）传感器（或设备）的读取头。 在一个示例中，读取头包括布置在与MR传感器相同水平的MR传感器和绝缘体层。 所述读取头还包括支承表面，其中所述绝缘体层形成所述支承表面的一部分并且设置在所述MR传感器的表面和所述支承表面之间，以提供所述MR传感器不受暴露于所述支承表面的保护。 MR传感器可以包括一叠薄膜层以形成AMR，GMR或TGMR传感器元件。 叠层还可包括倾斜表面部分，其中绝缘体层设置在倾斜表面部分上，从而将MR传感器从轴承表面凹入。

公开(公告)号：US07170721B2

公开(公告)日：2007-01-30

申请号：US10183329

申请日：2002-06-25

申请人： Andrew L. Wu

发明人： Andrew L. Wu

IPC分类号： G11B5/39 ,  G11B5/31

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G11B5/3133 ,  G11B5/3146 ,  G11B5/3916 ,  G11B5/40 ,  G11B5/4893 ,  G11B2005/3996

摘要： A flux guide protected magnetoresistive sensor in a tape drive read/write head is presented. The magnetoresistive sensor has a tape bearing surface, and includes a magnetoresistive sensing element and a flux guide disposed on a surface of the magnetoresistive sensing element to form a portion of the tape bearing surface.

摘要翻译： 介绍了磁带驱动读/写磁头中的磁通导向保护磁阻传感器。 磁阻传感器具有带状表面，并且包括磁阻感测元件和设置在磁阻感测元件的表面上以形成带状表面的一部分的磁通引导件。