公开(公告)号：US06432754B1

公开(公告)日：2002-08-13

申请号：US09788979

申请日：2001-02-20

申请人： Fariborz Assaderaghi ,  Tze-Chiang Chen ,  K. Paul Muller ,  Edward Joseph Nowak ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi

发明人： Fariborz Assaderaghi ,  Tze-Chiang Chen ,  K. Paul Muller ,  Edward Joseph Nowak ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L2100

CPC分类号： H01L29/78696 ,  H01L29/41733 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78618

摘要： The present invention provides various methods for forming a ground-plane SOI device which comprises at least a field effect transistor formed on a top Si-containing surface of a silicon-on-insulator (SOI) wafer; and an oxide region present beneath the field effect transistor, located in an area between source and drain regions which are formed in said SOI wafer, said oxide region is butted against shallow extensions formed in said SOI wafer, and is laterally adjacent to said source and drain regions.

摘要翻译： 本发明提供了用于形成接地平面SOI器件的各种方法，该器件至少包括形成在绝缘体上硅（SOI）晶片的顶部含Si表面上的场效应晶体管; 以及位于场效应晶体管下方的氧化物区域，位于形成在所述SOI晶片中的源极和漏极区域之间的区域中，所述氧化物区域与所述SOI晶片中形成的浅延伸区对接，并且与所述源极侧向相邻， 漏区。

公开(公告)号：US06657261B2

公开(公告)日：2003-12-02

申请号：US09757317

申请日：2001-01-09

申请人： Fariborz Assaderaghi ,  Tze-chiang Chen ,  K. Paul Muller ,  Edward J. Nowak ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Fariborz Assaderaghi ,  Tze-chiang Chen ,  K. Paul Muller ,  Edward J. Nowak ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L2701

CPC分类号： H01L29/66772 ,  H01L29/78603

摘要： A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.

公开(公告)号：US06521949B2

公开(公告)日：2003-02-18

申请号：US09848508

申请日：2001-05-03

申请人： Fariborz Assaderaghi ,  Tze-Chiang Chen ,  K. Paul Muller ,  Edward J. Nowak ,  Ghavam G. Shahidi

发明人： Fariborz Assaderaghi ,  Tze-Chiang Chen ,  K. Paul Muller ,  Edward J. Nowak ,  Ghavam G. Shahidi

IPC分类号： H01L2701

CPC分类号： H01L29/66757 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78675

摘要： Short channel effects are effectively suppressed by steep impurity concentration gradients which can be placed with improved accuracy of location and geometry while relaxing process tolerances by implanting impurities in a polysilicon seed adjacent a conduction channel of a transistor and diffusing impurities therefrom into the conduction channel. The polysilicon seed also allows the epitaxial growth of polysilicon source/drain contacts therefrom having a configuration which minimizes current density and path length therein while providing further mechanical advantages.

摘要翻译： 通过陡峭的杂质浓度梯度有效地抑制了短沟道效应，其可以通过在邻近晶体管的导电沟道的多晶硅种子中注入杂质并将杂质从其扩散到导通通道中而使放置过程公差的同时提高了位置和几何形状的精度而放置。 多晶硅种子还允许其中的多晶硅源极/漏极接触器的外延生长具有最小化其中的电流密度和路径长度的结构，同时提供进一步的机械优点。

公开(公告)号：US07282425B2

公开(公告)日：2007-10-16

申请号：US11046912

申请日：2005-01-31

申请人： Steven John Koester ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi

发明人： Steven John Koester ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/823807 ,  H01L21/02002 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/1203

摘要： A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

摘要翻译： 制造半导体衬底的方法包括在化合物半导体衬底上外延生长元素半导体层。 绝缘层沉积在元素半导体层的顶部上，以形成第一衬底。 第一衬底被晶片结合到单晶Si衬底上，使得绝缘层与单晶Si衬底结合。 半导体器件包括单晶衬底和形成在单晶衬底上的电介质层。 在介电层上形成半导体化合物，在半导体化合物附近形成与半导体化合物晶格匹配的元素半导体材料。

公开(公告)号：US06333532B1

公开(公告)日：2001-12-25

申请号：US09356295

申请日：1999-07-16

申请人： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

发明人： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

IPC分类号： H01L27108

CPC分类号： H01L27/10894 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76286 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/945 ,  Y10S257/904

摘要： A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep trench in bulk Si while forming merged logic regions on SOI.

摘要翻译： 描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑 如CMOS。 氧离子注入用于在所选择的深度处形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。 可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。 本发明克服了在形成SOI上的合并逻辑区域的同时形成具有在体Si中的深沟槽的存储电容器形成DRAM的问题。

公开(公告)号：US07504311B2

公开(公告)日：2009-03-17

申请号：US11762376

申请日：2007-06-13

申请人： Steven John Koester ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi

发明人： Steven John Koester ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/84

CPC分类号： H01L21/823807 ,  H01L21/02002 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/1203

摘要： A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

摘要翻译： 制造半导体衬底的方法包括在化合物半导体衬底上外延生长元素半导体层。 绝缘层沉积在元素半导体层的顶部上，以形成第一衬底。 第一衬底被晶片结合到单晶Si衬底上，使得绝缘层与单晶Si衬底结合。 半导体器件包括单晶衬底和形成在单晶衬底上的电介质层。 在介电层上形成半导体化合物，在半导体化合物附近形成与半导体化合物晶格匹配的元素半导体材料。

公开(公告)号：US06756257B2

公开(公告)日：2004-06-29

申请号：US09975435

申请日：2001-10-11

申请人： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

发明人： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

IPC分类号： H01L2100

CPC分类号： H01L27/10894 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76286 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/945 ,  Y10S257/904

摘要： A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

摘要翻译： 描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑 如CMOS。 氧离子注入用于在所选择的深度形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。 可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。 本发明克服了形成DRAM的存储电容器形成的体积为Si的深沟槽，同时在SOI上形成合并的逻辑区域的问题。

公开(公告)号：US06566198B2

公开(公告)日：2003-05-20

申请号：US09821520

申请日：2001-03-29

申请人： Heemyong Park ,  Fariborz Assaderaghi ,  Atul C. Ajmera ,  Ghavam G. Shahidi

发明人： Heemyong Park ,  Fariborz Assaderaghi ,  Atul C. Ajmera ,  Ghavam G. Shahidi

IPC分类号： H01L21336

CPC分类号： H01L29/78696 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66772 ,  H01L29/78684

摘要： A CMOS structure and method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. In the method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both the SOI and BOX interface. This allows for oxide spacer formation for gate-to-source/drain isolation which makes possible raised source/drain fabrication without increasing contact resistance.

摘要翻译： 在SOI上实现CMOS结构的自对准凸起源极/漏极的CMOS结构和方法，而不依赖于硅的选择性外延生长。 在该方法中，通过进行牺牲氧化来提供CMOS结构，使得在SOI和BOX界面的表面上发生氧化。 这允许用于栅极至源极/漏极隔离的氧化物间隔物形成，这使得可能的升高的源极/漏极制造而不增加接触电阻。

公开(公告)号：US06562666B1

公开(公告)日：2003-05-13

申请号：US09702314

申请日：2000-10-31

申请人： Heemyong Park ,  Fariborz Assaderaghi ,  Jack A. Mandelman ,  Ghavam G. Shahidi ,  Lawrence F. Wagner, Jr.

发明人： Heemyong Park ,  Fariborz Assaderaghi ,  Jack A. Mandelman ,  Ghavam G. Shahidi ,  Lawrence F. Wagner, Jr.

IPC分类号： H01L2100

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： Capacitance between source/drain and p-type substrate in SOI CMOS circuits is reduced by implanting an n-type layer below the oxide layer, thereby forming a fully depleted region that adds to the thickness of the oxide layer, while creating a junction capacitance region that reduces the total device to substrate capacitance.

摘要翻译： 在SOI CMOS电路中的源极/漏极和p型衬底之间的电容通过在氧化物层下方注入n型层来减少，从而形成增加氧化物层的厚度的完全耗尽区，同时产生结电容区 这将总体器件减少到衬底电容。

公开(公告)号：US07163866B2

公开(公告)日：2007-01-16

申请号：US10732277

申请日：2003-12-11

申请人： Fariborz Assaderaghi ,  Werner Rausch ,  Dominic Joseph Schepis ,  Ghavam G. Shahidi

发明人： Fariborz Assaderaghi ,  Werner Rausch ,  Dominic Joseph Schepis ,  Ghavam G. Shahidi

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/78612

摘要： Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.

摘要翻译： 通过在MOSFET的半导体SOI层的栅极下方和通道区域中提供铟的凹穴注入来解决SOI MOSFET的浮体的缺点。 还提供了用于制造该装置的方法。