公开(公告)号：US5559974A

公开(公告)日：1996-09-24

申请号：US459284

申请日：1995-06-02

申请人： Darrell D. Boggs ,  Gary L. Brown ,  Michael M. Hancock ,  Donald D. Parker

发明人： Darrell D. Boggs ,  Gary L. Brown ,  Michael M. Hancock ,  Donald D. Parker

IPC分类号： G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F9/22

CPC分类号： G06F9/30167 ,  G06F9/30145 ,  G06F9/35 ,  G06F9/3863

摘要： A decoder that includes a micro-alias register to store information from a micro-operation for use by later micro-operations in the micro-operation flow. The decoder includes one or more XLAT PLAs that produces PLA control micro-operations ("Cuops"), a microcode sequencing unit that produces microcode Cuops, and an aliasing mechanism that extracts fields and stores them in macro-alias registers. A multiplexer is provided to select the appropriate Cuop to be stored in a Cuop register. Multiple Cuops may issue each cycle. A multiplexer is coupled to select one of the Cuops and to store predetermined fields in the micro-alias register for use by subsequent Cuops. Micro-alias data and macro-alias data can be utilized simultaneously with a Cuop to form an Auop.

摘要翻译： 一种解码器，其包括微型别名寄存器，用于存储来自微操作的信息以供微操作流中的后续微操作使用。 解码器包括产生PLA控制微操作（“Cuops”）的一个或多个XLAT PLA，产生微代码Cuops的微代码排序单元，以及提取字段并将其存储在宏别名寄存器中的混叠机制。 提供多路复用器以选择要存储在Cuop寄存器中的适当Cuop。 多个Cuops可以发出每个周期。 多路复用器被耦合以选择Cuops中的一个并且将预定字段存储在微别名寄存器中以供随后的Cuops使用。 Micro-alias数据和宏别名数据可以与Cuop同时使用以形成Auop。

公开(公告)号：US5566298A

公开(公告)日：1996-10-15

申请号：US204744

申请日：1994-03-01

申请人： Darrell D. Boggs ,  Gary L. Brown ,  Michael M. Hancock ,  Donald D. Parker ,  Gail M. Rupnick

发明人： Darrell D. Boggs ,  Gary L. Brown ,  Michael M. Hancock ,  Donald D. Parker ,  Gail M. Rupnick

IPC分类号： G06F9/26 ,  G06F9/38 ,  G06F11/14 ,  G06F11/00 ,  G06F11/20

CPC分类号： G06F11/1407 ,  G06F9/268 ,  G06F9/3861

摘要： A state recovery and restart method that simplifies assist handling. The recovery and restart method also handles micro-branch mispredictions. An assist sequence is executed in microcode to assist an error-causing macroinstruction. If data is required from an error-causing macroinstruction, it is fetched, decoded, and macro-alias registers are restored with macro-alias data. To recover the state of the micro-alias registers, micro-alias data from a micro-operation of the flow may be loaded into the micro-alias register. Subsequently, control returns to the Micro-operation Sequence (MS) unit to issue further error correction Control micro-operations (Cuops). In order to simplify restart, the Cuops originating from the error-causing macroinstruction supplied by the translate programmable logic arrays (XLAT PLAs) are loaded into the Cuop registers, with their valid bits unasserted. If microcode requests a restart beginning at one of the Cuops stored in the Cuop register, then the bits for that Cuop and subsequent Cuops are marked valid. Thus, the instruction can be restarted anywhere within the microcode sequence.

摘要翻译： 一种简化辅助处理的状态恢复和重启方法。 恢复和重新启动方法也处理微分支错误预测。 在微代码中执行辅助序列以辅助引起错误的宏指令。 如果需要来自导致错误的宏指令的数据，则会获取，解码和使用宏别名数据恢复宏别名寄存器。 为了恢复微别名寄存器的状态，来自流程的微操作的微别名数据可以被加载到微别名寄存器中。 随后，控制返回到微操作序列（MS）单元以发出进一步的纠错控制微操作（Cuops）。 为了简化重新启动，由翻译可编程逻辑阵列（XLAT PLA）提供的引起误差的宏指令产生的钳位被加载到Cuop寄存器中，其有效位被置为无效。 如果微码请求从Cuop寄存器中存储的一个Cuops开始重新启动，那么该Cuop和后续Cuops的位将被标记为有效。 因此，可以在微代码序列内的任何地方重新启动指令。

公开(公告)号：US5581717A

公开(公告)日：1996-12-03

申请号：US204742

申请日：1994-03-01

申请人： Darrell D. Boggs ,  Gary L. Brown ,  Donald D. Parker

发明人： Darrell D. Boggs ,  Gary L. Brown ,  Donald D. Parker

IPC分类号： G06F9/22 ,  G06F9/30 ,  G06F9/302 ,  G06F9/35 ,  G06F9/34 ,  G06F9/40

CPC分类号： G06F9/3001 ,  G06F9/223 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/35

摘要： Decoding circuitry and a method supplying an immediate field that is issued from a decoder. A macroinstruction is supplied to the decoding circuit, which generates a first micro-operation that includes a first aliasing field and a first immediate field. The first aliasing field indicates the source of the micro-operation that will eventually be issued from the decoder. If the source is the first immediate field, then the alias field is further examined to determine the interpretation to be placed upon the data. The data may be interpreted literally, or as an address into a constant ROM, thereby providing an ability to output wide, 32-bit immediate data from a narrower, 9-bit input addresses. Additional sources for immediate data include macro-alias registers, macro-branch information, and micro-branch information.

摘要翻译： 解码电路和提供从解码器发出的立即字段的方法。 宏指令被提供给解码电路，其产生包括第一混叠字段和第一立即字段的第一微操作。 第一个混叠字段指示最终将从解码器发出的微操作的源。 如果源是第一个立即字段，则进一步检查别名字段以确定要放置在数据上的解释。 数据可以被字面地解释，或者作为一个地址到恒定的ROM中，从而提供从较窄的9位输入地址输出宽的32位立即数据的能力。 即时数据的其他来源包括宏别名寄存器，宏分支信息和微分支信息。

公开(公告)号：US6041403A

公开(公告)日：2000-03-21

申请号：US721900

申请日：1996-09-27

申请人： Donald D. Parker ,  Darrell D. Boggs ,  Alan B. Kyker

发明人： Donald D. Parker ,  Darrell D. Boggs ,  Alan B. Kyker

IPC分类号： G06F9/28 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/28 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A method and apparatus for decoding a macroinstruction, the macroinstruction including an operational code (opcode) and a specification of an operand, is described. The method includes two primary steps, which are performed either serially or in parallel. When performed serially, the steps may be performed in any order. The first primary step involves the generation of a first micro-instruction, specifying a first micro-operation, the first micro-instruction being derived from the specification of the operand of the macroinstruction. The second primary step involves the generation of a second micro-instruction, specifying a second micro-operation, the second micro-instruction being derived from the opcode of macroinstruction. The specification of the operand may specify the operand to be either a memory operand or a register operand in a manner that necessitates data processing or manipulation prior to a memory access or to execution of the second micro-instruction. More specifically, the specification of the operand in the macroinstruction may require alignment of operands retrieved from registers, prior to execution of the second instruction. In this case, the first micro-instruction may require a shift operation after retrieval of the operands.

摘要翻译： 描述了用于解码宏指令的方法和装置，包括操作代码（操作码）的宏指令和操作数的指定。 该方法包括串行或并行执行的两个主要步骤。 当连续执行时，可以以任何顺序执行步骤。 第一个主要步骤涉及产生第一个微指令，指定第一个微操作，第一个微指令是从宏指令的操作数的指定中导出的。 第二主要步骤涉及产生第二微指令，指定第二微操作，第二微指令是从宏指令的操作码导出的。 操作数的指定可以将操作数指定为存储器操作数或寄存器操作数，其方式是在存储器访问之前必须进行数据处理或操作，或执行第二微指令。 更具体地说，宏指令中的操作数的规范可能需要在执行第二指令之前对从寄存器检索的操作数的对齐。 在这种情况下，第一微指令可能需要在检索操作数之后进行移位操作。

公开(公告)号：US07216220B2

公开(公告)日：2007-05-08

申请号：US10891165

申请日：2004-07-14

申请人： Gary L Brown ,  Christopher S. Jones ,  Darrell D. Boggs

发明人： Gary L Brown ,  Christopher S. Jones ,  Darrell D. Boggs

IPC分类号： G06F9/44

CPC分类号： G06F9/3017 ,  G06F9/26

摘要： A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into the customer code store, at a time prior to its execution. The customer code store thus serves as a write-once execute-many library of pre-decoded routines which ISA level applications can subsequently use, permitting a system manufacturer to create a highly customized and optimized system.

摘要翻译： 包括存储器存储器的微处理器，ISA客户代码程序在被解码成其机器本机微指令之后可被存储到其中。 作为高速缓冲存储器，客户代码存储器不会被驱逐等等。 ISA级代码可以在执行之前指定一个用于存储到客户代码存储中的例程。 因此，客户代码存储库用作可以随后使用ISA级应用程序的预先解码的例程的一次写入的多执行程序库，允许系统制造商创建高度定制和优化的系统。

公开(公告)号：US07200737B1

公开(公告)日：2007-04-03

申请号：US09474096

申请日：1999-12-29

申请人： Amit A. Merchant ,  Darrell D. Boggs ,  David J. Sager

发明人： Amit A. Merchant ,  Darrell D. Boggs ,  David J. Sager

IPC分类号： G06F9/00

CPC分类号： G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3869

摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a replay queue coupled to the checker for temporarily storing one or more instructions for replay. The replay queue may be used to store a long latency instruction, such as a load in which data must be retrieved from an external memory device. The long latency instruction and possibly one or more dependent instruction are stored in the replay queue until the long latency instruction is ready to be executed (e.g., data for the load instruction has been retrieved from external memory). Once the long latency instruction is ready to be executed, (e.g., the data is available), the long latency instruction may then be unloaded from the replay queue for re-execution.

摘要翻译： 提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。 重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检查器的重放队列，用于临时存储用于重放的一个或多个指令。 重放队列可以用于存储长延迟指令，例如必须从外部存储器件检索数据的负载。 长延迟指令和可能的一个或多个相关指令被存储在重放队列中，直到长延迟指令准备好执行（例如，已从外部存储器检索到加载指令的数据）。 一旦长延迟指令准备好执行（例如，数据可用），则可以从重放队列卸载长延迟指令以便重新执行。

公开(公告)号：US07849465B2

公开(公告)日：2010-12-07

申请号：US11134687

申请日：2005-05-19

申请人： Xiang Zou ,  Hong Wang ,  Scott Dion Rodgers ,  Darrell D. Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry O. Smith ,  James B. Crossland ,  Chris J. Newburn

发明人： Xiang Zou ,  Hong Wang ,  Scott Dion Rodgers ,  Darrell D. Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry O. Smith ,  James B. Crossland ,  Chris J. Newburn

IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F7/38

CPC分类号： G06F9/3851 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/4843 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.

摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。 收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。 响应于条件，可以在操作系统的有限干预下激活服务线程。 在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。 该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。 可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。 还描述和要求保护其他实施例。

公开(公告)号：US06467027B1

公开(公告)日：2002-10-15

申请号：US09475746

申请日：1999-12-30

申请人： Alan B. Kyker ,  Darrell D. Boggs

发明人： Alan B. Kyker ,  Darrell D. Boggs

IPC分类号： G06F1200

CPC分类号： G06F9/3812 ,  G06F12/0875

摘要： A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.

摘要翻译： 一种用于使用使用字段来维护在流水线处理器中的指令的方法。 该方法包括接收对指令的读取请求，响应于读取请求发送指令并设置与该指令相关联的使用字段以使用。 该方法的替代实施例涉及响应于读请求发送指令，接收指令退出通知并重置ITLB中的使用字段。 该方法也可以用在ICACHE中，其中使用字段与存储在ICACHE中的每个指令相关联。 该方法的其他实施例可以在ITLB和ICACHE中同时使用作为资源跟踪机制来维护资源。

公开(公告)号：US5463745A

公开(公告)日：1995-10-31

申请号：US174074

申请日：1993-12-22

申请人： Rohit A. Vidwans ,  Darrell D. Boggs ,  Michael A. Fetterman ,  Andrew F. Glew

发明人： Rohit A. Vidwans ,  Darrell D. Boggs ,  Michael A. Fetterman ,  Andrew F. Glew

IPC分类号： G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Instructions are fetched and issued by an instruction fetch and issue circuit with the instructions' sizes in program order. An allocate circuit allocates reservation station entries in a reservation station circuit, and reorder buffer entries in a reorder circuit, for the issued instructions in order, storing the instructions' sizes in the allocated reorder buffer entries. The reservation and dispatch circuit dispatches the issued instructions to the execution circuits for execution when they are ready. The execution circuits store the result data including target addresses of branch instructions into the corresponding reorder buffer entries. During each retirement operation, a retire circuit reads the instruction sizes and the target addresses for a predetermined number of issued instructions from their allocated reorder buffer entries. The retire circuit determines two or more speculative next instruction pointers for each of the issued instructions, factoring into consideration whether the issued instructions are branch instructions or not, and their relative positions to each other. Each of the speculative next instruction pointers indicates what the next instruction pointer for the processor should be for retiring a particular combination of the result data values of the issued instructions under consideration. The retire circuit conditionally updates the next instruction pointer with one of the speculative next instruction pointers, depending on how many, if any, of the instructions can actually retire, and whether any of the actually retiring instructions are branch instructions.

摘要翻译： 指令由指令提取和发布电路以指令的大小以程序顺序取出并发出。 分配电路在保留站电路中分配保留站条目，并且重新排序重新排序电路中的缓冲区条目，以便按顺序发布指令，将指令的大小存储在所分配的重排序缓冲器条目中。 预约和调度电路在准备就绪时将发出的指令发送到执行电路执行。 执行电路将包括分支指令的目标地址的结果数据存储到相应的重排序缓冲器条目中。 在每个退休操作期间，退出电路从其分配的重排序缓冲器条目读取预定数量的已发布指令的指令大小和目标地址。 退出电路为每个发出的指令确定两个或更多个推测下一个指令指针，考虑所发出的指令是否是分支指令，以及它们彼此的相对位置。 每个推测下一个指令指针指示处理器的下一个指令指针应该用于退出所考虑的已发出指令的结果数据值的特定组合。 退出电路有条件地使用推测下一个指令指针之一更新下一个指令指针，这取决于指令实际可以退出多少（如果有的话），以及是否有任何实际退出的指令是分支指令。

公开(公告)号：US07219349B2

公开(公告)日：2007-05-15

申请号：US10792154

申请日：2004-03-02

申请人： Amit A. Merchant ,  Darrell D. Boggs ,  David J. Sager

发明人： Amit A. Merchant ,  Darrell D. Boggs ,  David J. Sager

IPC分类号： G06F9/46 ,  G06F9/40 ,  G06F15/76

CPC分类号： G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3869

摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.

摘要翻译： 提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。 重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。 在一个实施例中，线程特定的重播队列部分可以各自用于存储每个线程的长等待时间指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。 通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。