Photomask and integrated circuit manufactured by automatically eliminating design rule violations during construction of a mask layout block
    1.
    发明申请
    Photomask and integrated circuit manufactured by automatically eliminating design rule violations during construction of a mask layout block 失效
    光掩模和集成电路通过在构造掩模布局块期间自动消除设计规则违规而制造

    公开(公告)号:US20020166109A1

    公开(公告)日:2002-11-07

    申请号:US10180865

    申请日:2002-06-26

    IPC分类号: G06F017/50

    CPC分类号: G06F17/5081

    摘要: A photomask and integrated circuit manufactured by eliminating design rule violations during construction of a mask layout block are disclosed. A photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a selected position for a polygon in a mask layout block, identifying a design rule violation in the mask layout block if the selected position is less than a design rule from a technology file, and automatically preventing the polygon from being placed in the mask layout block at the selected position if the design rule violation is identified.

    摘要翻译: 公开了通过在构造掩模布局块期间消除设计规则违规而制造的光掩模和集成电路。 光掩模包括衬底和形成在衬底的至少一部分上的图案层。 图案化层可以使用通过分析掩模布局块中的多边形的选定位置而创建的掩模图案文件,如果所选择的位置小于来自技术文件的设计规则,则识别掩模布局块中的设计规则违反 并且如果识别出设计规则冲突,则自动地防止多边形被放置在所选位置的掩模布局块中。

    System and method for eliminating design rule violations during construction of a mask layout block
    2.
    发明申请
    System and method for eliminating design rule violations during construction of a mask layout block 失效
    在构造掩模布局块期间消除设计规则违规的系统和方法

    公开(公告)号:US20020166103A1

    公开(公告)日:2002-11-07

    申请号:US10180177

    申请日:2002-06-26

    IPC分类号: G06F017/50

    CPC分类号: G06F17/5081

    摘要: A system and method for eliminating design rule violations during construction of a mask layout block are disclosed. The method includes analyzing a selected position for a polygon in a mask layout block and obtaining one or more design rules associated with the polygon from a technology file. The method provides a hint area associated with the selected position for the polygon that graphically represents a space in the mask layout block where the selected position complies with the design rule violation.

    摘要翻译: 公开了一种用于在构造掩模布局块期间消除设计规则违规的系统和方法。 该方法包括在掩模布局块中分析多边形的选定位置,并从技术文件获得与多边形相关联的一个或多个设计规则。 该方法提供与多边形的所选位置相关联的提示区域,其图形地表示掩模布局块中的空间,其中所选位置符合设计规则违规。

    Varible surface hot plate for improved bake uniformity of substrates
    3.
    发明申请
    Varible surface hot plate for improved bake uniformity of substrates 失效
    可变表面热板,用于提高基材的烘烤均匀性

    公开(公告)号:US20020086248A1

    公开(公告)日:2002-07-04

    申请号:US09990791

    申请日:2001-11-16

    摘要: A system, method and apparatus are described for improving critical dimension uniformity in baked substrates. The system, method and apparatus provide for varying the distance between a substrate to be baked and the surface of a hot plate such that an approximately uniform temperature is obtained in the substrate during baking. In one embodiment, the substrate is positioned on a hot plate having a recess generally centered on its top side. The differences in distance between the edges of the substrates contacting the hot plate and the distance between the center region of the substrate and the bottom of the recess enable a generally uniform temperature to be obtained in the substrate.

    摘要翻译: 描述了一种系统,方法和装置,用于改善焙烧基材中的临界尺寸均匀性。 该系统,方法和装置提供了改变要烘烤的基材和热板的表面之间的距离,使得在烘烤期间在基材中获得大致均匀的温度。 在一个实施例中,基板定位在热板上,该热板具有通常以其顶侧为中心的凹槽。 接触热板的基板的边缘与基板的中心区域与凹部的底部之间的距离的差异使得能够在基板中获得大致均匀的温度。

    Photomask and integrated circuit manufactured by automatically correcting design rule violations in a mask layout file
    4.
    发明申请
    Photomask and integrated circuit manufactured by automatically correcting design rule violations in a mask layout file 失效
    光掩模和集成电路通过自动校正掩模布局文件中的设计规则违规而制造

    公开(公告)号:US20020152453A1

    公开(公告)日:2002-10-17

    申请号:US10161527

    申请日:2002-06-03

    发明人: Dan Rittman

    IPC分类号: G06F017/50

    CPC分类号: G06F17/5081 G03F1/36

    摘要: A photomask and method for eliminating design rule violations from the photomask are disclosed. A photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by comparing a feature dimension in a mask layout file with a design rule in a technology file, identifying a design rule violation if the feature dimension is less than the design rule and automatically correcting the identified design rule violation in the mask layout file.

    摘要翻译: 公开了一种用于从光掩模中消除违反设计规则的光掩模和方法。 光掩模包括衬底和形成在衬底的至少一部分上的图案层。 图案化层可以使用通过将掩模布局文件中的特征尺寸与技术文件中的设计规则进行比较而创建的掩模图案文件来形成,如果特征尺寸小于设计规则,则识别设计规则违反,并且自动校正 在面具布局文件中识别设计规则违规。

    Variable surface hot plate for improved bake uniformity of substrates
    5.
    发明申请
    Variable surface hot plate for improved bake uniformity of substrates 失效
    可变表面热板,用于提高基材的烘烤均匀性

    公开(公告)号:US20020092843A1

    公开(公告)日:2002-07-18

    申请号:US10073711

    申请日:2002-02-11

    IPC分类号: F27D011/00 H05B003/68

    摘要: A system, method and apparatus are described for improving critical dimension uniformity in baked substrates. The system, method and apparatus provide for varying the distance between a substrate to be baked and the surface of a hot plate such that an approximately uniform temperature is obtained in the substrate during baking. In one embodiment, the substrate is positioned on a hot plate having a recess generally centered on its top side. The differences in distance between the edges of the substrates contacting the hot plate and the distance between the center region of the substrate and the bottom of the recess enable a generally uniform temperature to be obtained in the substrate.

    摘要翻译: 描述了一种系统,方法和装置,用于改善焙烧基材中的临界尺寸均匀性。 该系统,方法和装置提供了改变要烘烤的基材和热板的表面之间的距离,使得在烘烤期间在基材中获得大致均匀的温度。 在一个实施例中,基板定位在热板上,该热板具有通常以其顶侧为中心的凹槽。 接触热板的基板的边缘与基板的中心区域与凹部的底部之间的距离的差异使得能够在基板中获得大致均匀的温度。

    Test wafer and method for investigating electrostatic discharge induced wafer defects
    6.
    发明申请
    Test wafer and method for investigating electrostatic discharge induced wafer defects 失效
    测试晶片和调查静电放电诱发晶片缺陷的方法

    公开(公告)号:US20020076840A1

    公开(公告)日:2002-06-20

    申请号:US10071167

    申请日:2002-02-08

    发明人: Andreas Englisch

    IPC分类号: H01L021/66

    CPC分类号: H01L22/34 G03F1/40 G03F1/84

    摘要: A test wafer and method for investigating electrostatic discharge induced wafer defects are disclosed. The test wafer includes an electrostatic discharge (ESD) sensitive risk scale geometry, formed thereon. After exposure to a semiconductor manufacturing procedure, the test wafer may be analyzed by using the ESD risk scale geometry to identify and evaluate severity of any ESD effects associated with the semiconductor manufacturing procedure.

    摘要翻译: 公开了用于研究静电放电感应晶片缺陷的测试晶片和方法。 测试晶片包括在其上形成的静电放电(ESD)敏感的风险标度几何形状。 在暴露于半导体制造程序之后,可以通过使用ESD风险等级几何来分析测试晶片,以识别和评估与半导体制造过程相关的任何ESD效应的严重性。

    System and method for correcting connectivity errors in a mask layout file
    7.
    发明申请
    System and method for correcting connectivity errors in a mask layout file 失效
    用于校正掩码布局文件中的连接错误的系统和方法

    公开(公告)号:US20020166108A1

    公开(公告)日:2002-11-07

    申请号:US10132776

    申请日:2002-04-25

    发明人: Dan Rittman

    IPC分类号: G06F017/50

    CPC分类号: G06F17/5081

    摘要: A system and method for correcting connectivity errors in a mask layout are disclosed. The method includes comparing a first connection in a mask layout file to a second connection in a schematic netlist. A connectivity error is identified if the first connection does not match the second connection and the identified connectivity error is automatically corrected in the mask layout file.

    摘要翻译: 公开了一种用于校正掩模布局中的连通性错误的系统和方法。 该方法包括将掩模布局文件中的第一连接与原理图网表中的第二连接进行比较。 如果第一个连接与第二个连接不匹配,并且识别的连接错误在掩码布局文件中自动更正,则会识别连接错误。