摘要:
A photomask and integrated circuit manufactured by eliminating design rule violations during construction of a mask layout block are disclosed. A photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a selected position for a polygon in a mask layout block, identifying a design rule violation in the mask layout block if the selected position is less than a design rule from a technology file, and automatically preventing the polygon from being placed in the mask layout block at the selected position if the design rule violation is identified.
摘要:
A system and method for eliminating design rule violations during construction of a mask layout block are disclosed. The method includes analyzing a selected position for a polygon in a mask layout block and obtaining one or more design rules associated with the polygon from a technology file. The method provides a hint area associated with the selected position for the polygon that graphically represents a space in the mask layout block where the selected position complies with the design rule violation.
摘要:
A system, method and apparatus are described for improving critical dimension uniformity in baked substrates. The system, method and apparatus provide for varying the distance between a substrate to be baked and the surface of a hot plate such that an approximately uniform temperature is obtained in the substrate during baking. In one embodiment, the substrate is positioned on a hot plate having a recess generally centered on its top side. The differences in distance between the edges of the substrates contacting the hot plate and the distance between the center region of the substrate and the bottom of the recess enable a generally uniform temperature to be obtained in the substrate.
摘要:
A photomask and method for eliminating design rule violations from the photomask are disclosed. A photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by comparing a feature dimension in a mask layout file with a design rule in a technology file, identifying a design rule violation if the feature dimension is less than the design rule and automatically correcting the identified design rule violation in the mask layout file.
摘要:
A system, method and apparatus are described for improving critical dimension uniformity in baked substrates. The system, method and apparatus provide for varying the distance between a substrate to be baked and the surface of a hot plate such that an approximately uniform temperature is obtained in the substrate during baking. In one embodiment, the substrate is positioned on a hot plate having a recess generally centered on its top side. The differences in distance between the edges of the substrates contacting the hot plate and the distance between the center region of the substrate and the bottom of the recess enable a generally uniform temperature to be obtained in the substrate.
摘要:
A test wafer and method for investigating electrostatic discharge induced wafer defects are disclosed. The test wafer includes an electrostatic discharge (ESD) sensitive risk scale geometry, formed thereon. After exposure to a semiconductor manufacturing procedure, the test wafer may be analyzed by using the ESD risk scale geometry to identify and evaluate severity of any ESD effects associated with the semiconductor manufacturing procedure.
摘要:
A system and method for correcting connectivity errors in a mask layout are disclosed. The method includes comparing a first connection in a mask layout file to a second connection in a schematic netlist. A connectivity error is identified if the first connection does not match the second connection and the identified connectivity error is automatically corrected in the mask layout file.