公开(公告)号：US07566919B2

公开(公告)日：2009-07-28

申请号：US10581639

申请日：2004-12-09

申请人： Johannes Josephus Theodorus Marinus Donkers ,  Petrus Hubertus Cornelis Magnee ,  Eddy Kunnen ,  Francois Igor Neuilly

发明人： Johannes Josephus Theodorus Marinus Donkers ,  Petrus Hubertus Cornelis Magnee ,  Eddy Kunnen ,  Francois Igor Neuilly

IPC分类号： H01L21/20

CPC分类号： H01L21/8249 ,  H01L29/66242 ,  H01L29/66272

摘要： A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region (12) adjacent to an active silicon region (10); forming a silicon nitride/silicon stack (14, 16) above the field isolation oxide region (12), wherein the silicon nitride/silicon stack (14, 16) includes a top layer of silicon (14) and a bottom layer of silicon nitride (16); performing an etch to the silicon nitride/silicon stack (14, 16) to form a stepped seed layer, wherein the top layer of silicon is etched laterally at the same time the bottom layer of silicon nitride is etched; and growing an Si/SiGe/Si stack (20) over the stepped seed layer and active region (10).

摘要翻译： 一种在双极器件中形成外延基底层的方法。 该方法包括以下步骤：提供具有与有源硅区域（10）相邻的场隔离氧化物区域（12）的结构; 在所述场隔离氧化物区域（12）上形成氮化硅/硅堆叠（14,16），其中所述氮化硅/硅堆叠（14,16）包括硅顶层（14）和底层氮化硅 （16）; 对所述氮化硅/硅堆叠（14,16）进行蚀刻以形成阶梯式种子层，其中在蚀刻所述底层氮化硅的同时侧向蚀刻所述硅顶层; 以及在所述阶梯式种子层和有源区域（10）上生长Si / SiGe / Si堆叠（20）。

公开(公告)号：US07396732B2

公开(公告)日：2008-07-08

申请号：US11048642

申请日：2005-01-31

申请人： Eddy Kunnen

发明人： Eddy Kunnen

IPC分类号： H01L21/8228

CPC分类号： H01L21/76898 ,  H01L21/762 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1094 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

摘要翻译： 公开了一种用于在半导体衬底中形成深沟槽或通孔气隙的方法，包括以下步骤：在衬底中图案化孔，部分地用牺牲材料（例如多晶硅）填充所述孔，在未填充部分的侧壁上沉积间隔物 （例如TEOS）以缩小开口，通过所述变窄的开口去除牺牲材料的剩余部分（例如通过各向同性蚀刻），并最终通过在间隔物上方沉积保形层（TEOS）来密封气隙的开口。 成功构建气隙的方法成功应用于BiCMOS器件中的深沟槽隔离结构。

公开(公告)号：US20060223301A1

公开(公告)日：2006-10-05

申请号：US11305421

申请日：2005-12-16

申请人： Serge Vanhaelemeersch ,  Eddy Kunnen ,  Laure Carbonell

发明人： Serge Vanhaelemeersch ,  Eddy Kunnen ,  Laure Carbonell

IPC分类号： H01L21/4763

CPC分类号： H01L21/76898 ,  H01L21/762 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1094 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.

摘要翻译： 公开了一种用于在半导体衬底中形成深通孔气孔的方法，包括以下步骤：在衬底中图案化孔，部分地用牺牲材料（例如多晶硅）填充所述孔，在所述衬底的未填充部分的侧壁上形成间隔物 孔（例如TEOS）以缩小开口，通过所述变窄的开口去除牺牲材料的剩余部分（例如通过各向同性蚀刻），并且最后通过在间隔物上方沉积保形层（TEOS）来密封气隙的开口。 形成深通孔气隙的方法用于产生晶片到晶片垂直堆叠。 在完成传统的FEOL和BEOL处理之后，晶片的背面将变薄，使得深通孔气隙被打开，并且导电材料可以通过开口沉积在所述（气隙）内，并且通过填充导电材料的穿透晶片或深通孔被产生 。

公开(公告)号：US20060131655A1

公开(公告)日：2006-06-22

申请号：US11048642

申请日：2005-01-31

申请人： Eddy Kunnen

发明人： Eddy Kunnen

IPC分类号： H01L29/94 ,  H01L21/4763

CPC分类号： H01L21/76898 ,  H01L21/762 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1094 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

公开(公告)号：US07400024B2

公开(公告)日：2008-07-15

申请号：US11408100

申请日：2006-04-20

申请人： Eddy Kunnen

发明人： Eddy Kunnen

IPC分类号： H01L29/00

CPC分类号： H01L21/76898 ,  H01L21/762 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1094 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

公开(公告)号：US20060258077A1

公开(公告)日：2006-11-16

申请号：US11408100

申请日：2006-04-20

申请人： Eddy Kunnen

发明人： Eddy Kunnen

IPC分类号： H01L21/8238 ,  H01L29/80

CPC分类号： H01L21/76898 ,  H01L21/762 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1094 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

摘要翻译： 公开了一种用于在半导体衬底中形成深沟槽或通孔气隙的方法，包括以下步骤：在衬底中图案化孔，部分地用牺牲材料（例如多晶硅）填充所述孔，在未填充部分的侧壁上沉积间隔物 （例如TEOS）以缩小开口，通过所述变窄的开口去除牺牲材料的剩余部分（例如通过各向同性蚀刻），并最终通过在间隔物上方沉积保形层（TEOS）来密封气隙的开口。 成功构建气隙的方法成功应用于BiCMOS器件中的深沟槽隔离结构。

公开(公告)号：US20050189318A1

公开(公告)日：2005-09-01

申请号：US11045954

申请日：2005-01-28

申请人： Twan Bearda ,  Eddy Kunnen

发明人： Twan Bearda ,  Eddy Kunnen

IPC分类号： B81B1/00 ,  C23F1/00 ,  H01L21/033 ,  H01L21/302 ,  H01L21/308 ,  H01L21/44 ,  H01L21/461 ,  H01L21/762 ,  H01L33/22

CPC分类号： B81C1/00031 ,  B81B1/002 ,  B81C2201/0115 ,  H01L21/0331 ,  H01L21/0337 ,  H01L21/3086 ,  H01L33/22 ,  Y10S438/96

摘要： A method for forming macropores in a substrate is disclosed. On a substrate a pattern of submicron features is formed. This pattern is covered with a layer, which is preferably selectively removable with respect to the substrate and the submicron features. This cover layer is removed until the submicron features are exposed. The submicron features are then etched selectively to the cover layer, thereby creating a pattern of submicron openings in this cover layer. The patterned cover layer is used as a hardmask to etch macropores in the substrate.

摘要翻译： 公开了一种在衬底中形成大孔的方法。 在衬底上形成亚微米特征的图案。 该图案被层覆盖，该层优选地相对于基底和亚微米特征可选择性地移除。 去除该覆盖层，直到亚微米特征暴露。 然后将亚微米特征选择性地蚀刻到覆盖层，从而在该覆盖层中产生亚微米开口的图案。 图案化覆盖层用作硬掩模以蚀刻基底中的大孔。

公开(公告)号：US07338896B2

公开(公告)日：2008-03-04

申请号：US11305421

申请日：2005-12-16

申请人： Serge Vanhaelemeersch ,  Eddy Kunnen ,  Laure Elisa Carbonell

发明人： Serge Vanhaelemeersch ,  Eddy Kunnen ,  Laure Elisa Carbonell

IPC分类号： H01L21/46 ,  H01L21/4763

CPC分类号： H01L21/76898 ,  H01L21/762 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1094 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.

摘要翻译： 公开了一种用于在半导体衬底中形成深通孔气孔的方法，包括以下步骤：在衬底中图案化孔，部分地用牺牲材料（例如多晶硅）填充所述孔，在所述衬底的未填充部分的侧壁上形成间隔物 孔（例如TEOS）以缩小开口，通过所述变窄的开口去除牺牲材料的剩余部分（例如通过各向同性蚀刻），并且最后通过在间隔物上方沉积保形层（TEOS）来密封气隙的开口。 形成深通孔气隙的方法用于产生晶片到晶片垂直堆叠。 在完成传统的FEOL和BEOL处理之后，晶片的背面将变薄，使得深通孔气隙被打开，并且导电材料可以通过开口沉积在所述（气隙）内，并且通过填充导电材料的穿透晶片或深通孔被产生 。

公开(公告)号：US07060587B2

公开(公告)日：2006-06-13

申请号：US11045954

申请日：2005-01-28

申请人： Twan Bearda ,  Eddy Kunnen

发明人： Twan Bearda ,  Eddy Kunnen

IPC分类号： H01L21/76

CPC分类号： B81C1/00031 ,  B81B1/002 ,  B81C2201/0115 ,  H01L21/0331 ,  H01L21/0337 ,  H01L21/3086 ,  H01L33/22 ,  Y10S438/96

摘要： A method for forming macropores in a substrate is disclosed. On a substrate a pattern of submicron features is formed. This pattern is covered with a layer, which is preferably selectively removable with respect to the substrate and the submicron features. This cover layer is removed until the submicron features are exposed. The submicron features are then etched selectively to the cover layer, thereby creating a pattern of submicron openings in this cover layer. The patterned cover layer is used as a hardmask to etch macropores in the substrate.

摘要翻译： 公开了一种在衬底中形成大孔的方法。 在衬底上形成亚微米特征的图案。 该图案被层覆盖，该层优选地相对于基底和亚微米特征可选择性地移除。 去除该覆盖层，直到亚微米特征暴露。 然后将亚微米特征选择性地蚀刻到覆盖层，从而在该覆盖层中产生亚微米开口的图案。 图案化覆盖层用作硬掩模以蚀刻基底中的大孔。