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    Method for fabricating Tungsten local interconnections in high density CMOS circuits
    2.
    发明授权
    Method for fabricating Tungsten local interconnections in high density CMOS circuits 失效
    在高密度CMOS电路中制造钨局部互连的方法

    公开(公告)号：US5882992A

    公开(公告)日：1999-03-16

    申请号：US751673

    申请日：1996-11-18

    申请人： Edward Kobeda ,  Jeffrey Peter Gambino ,  George Gordon Gifford ,  Nickolas Joseph Mazzeo

    发明人： Edward Kobeda ,  Jeffrey Peter Gambino ,  George Gordon Gifford ,  Nickolas Joseph Mazzeo

    IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/4763

    CPC分类号： H01L21/76895

    摘要： The present invention provides a method for fabricating tungsten local interconnections in high density CMOS circuits, and also provides high density CMOS circuits having local interconnections formed of tungsten. Pursuant to the method, an etch stop layer of chromium is initially deposited on the circuit elements of the CMOS silicon substrate. Next, a conductive layer of tungsten is non-selectively deposited on the chromium layer. A photoresist mask is then lithographically patterned over the tungsten layer. The tungsten layer is then etched down to, and stopping at, the chromium layer, after which the photoresist mask is stripped. The stripping preferably uses a low temperature plasma etch in O.sub.2 at a temperature of less than 100.degree. C. Finally, a directional O.sub.2 reactive ion etch is used to remove the chromium layer selectively to the silicon substrate. Borderless contacts are formed with the aid of the chromium etch stop layer beneath the tungsten local interconnection layer. The method of integration of this approach results in anisotropic metal lines patterned over topography using a standard photoresist mask. This approach also allows partial overlap of contacts to reduce device dimensions, and thereby results in improved density and performance.

    摘要翻译： 本发明提供一种用于在高密度CMOS电路中制造钨局部互连的方法，并且还提供具有由钨形成的局部互连的高密度CMOS电路。 根据该方法，最初在CMOS硅衬底的电路元件上沉积铬的蚀刻停止层。 接下来，钨层的导电层被非选择性地沉积在铬层上。 然后光致抗蚀剂掩模在钨层上被光刻图案化。 然后将钨层蚀刻到铬层上并停止在其上，之后剥离光致抗蚀剂掩模。 剥离优选在低于100℃的温度下在O 2中使用低温等离子体蚀刻。最后，使用定向O 2反应离子蚀刻来选择性地将硅层除去到硅衬底。 借助于钨局部互连层下方的铬蚀刻停止层形成无边界接触。 该方法的集成方法导致使用标准光致抗蚀剂掩模在地形图上形成的各向异性金属线。 该方法还允许触点的部分重叠以减少器件尺寸，从而导致改善的密度和性能。

    SYSTEM AND STORAGE MEDIUM FOR PROVIDING AN END-TO-END BUSINESS PROCESS FOR ELECTRONIC SUPPLIER QUALIFICATION AND QUALITY MANAGEMENT
    3.
    发明申请
    SYSTEM AND STORAGE MEDIUM FOR PROVIDING AN END-TO-END BUSINESS PROCESS FOR ELECTRONIC SUPPLIER QUALIFICATION AND QUALITY MANAGEMENT 审中-公开
    用于提供电子供应商资质和质量管理的终端业务流程的系统和存储介质

    公开(公告)号：US20080162226A1

    公开(公告)日：2008-07-03

    申请号：US11968430

    申请日：2008-01-02

    申请人： John S. Maresca ,  Robert D. Hayes ,  Brent R. Jensen ,  Edward Kobeda ,  Eric T. Lambert ,  Katherine J. Pearsall ,  Benjamin J. Steele ,  Michael J. Whitney ,  Paul A. Zulpa

    发明人： John S. Maresca ,  Robert D. Hayes ,  Brent R. Jensen ,  Edward Kobeda ,  Eric T. Lambert ,  Katherine J. Pearsall ,  Benjamin J. Steele ,  Michael J. Whitney ,  Paul A. Zulpa

    IPC分类号： G06F17/40

    CPC分类号： G06Q99/00 ,  G06Q10/06395

    摘要： A system for facilitating supplier qualification and quality management functions includes an application executing on a host system and a web-based user interface provided by the application, the web-based user interface collaboratively enabling qualification of suppliers, parts, and technologies over a network. The system also includes a shared data repository and a workstation in communication with the host system, and a supplier in communication with the host system via the user interface and network. The collaborative qualification includes acquiring supplier capabilities, part data, and supplier technology data from a collaborative source via the user interface. The collaborative qualification also includes storing acquired data in the shared data repository, and performing quality management functions via the user interface and shared data repository. The quality management functions include: managing changes to a supplier product; managing process changes proposed by a supplier; and assessing quality metrics provided by a supplier.

    摘要翻译： 用于促进供应商资格和质量管理功能的系统包括在主机系统上执行的应用程序和由应用程序提供的基于Web的用户界面，基于网络的用户界面协同地实现通过网络鉴定供应商，部件和技术。 该系统还包括共享数据存储库和与主机系统通信的工作站，以及通过用户界面和网络与主机系统通信的供应商。 合作资质包括通过用户界面从合作来源获取供应商能力，部件数据和供应商技术数据。 协作资格还包括将获取的数据存储在共享数据存储库中，并通过用户界面和共享数据存储库执行质量管理功能。 质量管理职能包括：管理供应商产品的变更; 管理供应商提出的流程变更; 并评估供应商提供的质量指标。

    Method for fabricating tungsten local interconnections in high density CMOS
    6.
    发明授权
    Method for fabricating tungsten local interconnections in high density CMOS 失效
    在高密度CMOS中制造钨局部互连的方法

    公开(公告)号：US5338702A

    公开(公告)日：1994-08-16

    申请号：US9511

    申请日：1993-01-27

    申请人： Edward Kobeda ,  Jeffrey P. Gambino ,  George G. Gifford ,  Nickolas J. Mazzeo

    发明人： Edward Kobeda ,  Jeffrey P. Gambino ,  George G. Gifford ,  Nickolas J. Mazzeo

    IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L21/302

    CPC分类号： H01L21/32136 ,  H01L21/31138 ,  H01L21/76895 ,  Y10S438/97

    摘要： The present invention provides a method for fabricating tungsten local interconnections in high density CMOS circuits, and also provides high density CMOS circuits having local interconnections formed of tungsten. Pursuant to the method, an etch stop layer of chromium is initially deposited on the circuit elements of the CMOS silicon substrate. Next, a conductive layer of tungsten is non-selectively deposited on the chromium layer. A photoresist mask is then lithographically patterned over the tungsten layer. The tungsten layer is then etched down to, and stopping at, the chromium layer, after which the photoresist mask is stripped. The stripping preferably uses a low temperature plasma etch in O.sub.2 at a temperature of less than 100.degree. C. Finally, a directional O.sub.2 reactive ion etch is used to remove the chromium layer selectively to the silicon substrate. Borderless contacts are formed with the aid of the chromium etch stop layer beneath the tungsten local interconnection layer. The method of integration of this approach results in anisotropic metal lines patterned over topography using a standard photoresist mask. This approach also allows partial overlap of contacts to reduce device dimensions, and thereby results in improved density and performance.

    摘要翻译： 本发明提供一种用于在高密度CMOS电路中制造钨局部互连的方法，并且还提供具有由钨形成的局部互连的高密度CMOS电路。 根据该方法，最初在CMOS硅衬底的电路元件上沉积铬的蚀刻停止层。 接下来，钨层的导电层被非选择性地沉积在铬层上。 然后光致抗蚀剂掩模在钨层上被光刻图案化。 然后将钨层蚀刻到铬层上并停止在其上，之后剥离光致抗蚀剂掩模。 剥离优选在低于100℃的温度下在O 2中使用低温等离子体蚀刻。最后，使用定向O 2反应离子蚀刻来选择性地将硅层除去到硅衬底。 借助于钨局部互连层下方的铬蚀刻停止层形成无边界接触。 该方法的集成方法导致使用标准光致抗蚀剂掩模在地形图上形成的各向异性金属线。 该方法还允许触点的部分重叠以减少器件尺寸，从而导致改善的密度和性能。

    Method for fabricating bipolar and CMOS devices in integrated circuits using contact metallization for local interconnect and via landing
    7.
    发明授权
    Method for fabricating bipolar and CMOS devices in integrated circuits using contact metallization for local interconnect and via landing 失效
    在使用接触金属化用于局部互连和通过着陆的集成电路中制造双极和CMOS器件的方法

    公开(公告)号：US5208170A

    公开(公告)日：1993-05-04

    申请号：US761596

    申请日：1991-09-18

    申请人： Edward Kobeda ,  Gary L. Patton

    发明人： Edward Kobeda ,  Gary L. Patton

    IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L21/76895 ,  H01L21/32139 ,  H01L21/76801 ,  H01L21/76823 ,  H01L21/76834 ,  H01L21/76889

    摘要： A method for fabricating bipolar and CMOS devices in integrated circuits using W as a local interconnect and via landing pad for bipolar and CMOS devices. The method includes the forming of an oxide/silicon bilayer above a local interconnect of tungsten/titanium wherein the oxide is patterned as a mask for the silicon/tungsten/titanium reactive ion etch, and the silicon layer above the tungsten/titanium layer is used as an etch stop for a via etch. The silicon layer is then reacted and converted to titanium silicide after the via etch to provide a low resistance path in the via from the local interconnect in a self aligned manner.

    摘要翻译： 在使用W作为局部互连的集成电路中制造双极和CMOS器件的方法，以及用于双极和CMOS器件的着陆焊盘。 该方法包括在钨/钛的局部互连上方形成氧化物/硅双层，其中氧化物被图案化为硅/钨/钛反应离子蚀刻的掩模，并且使用钨/钛层上方的硅层 作为通孔蚀刻的蚀刻停止。 然后在通孔蚀刻之后使硅层反应并转化为硅化钛，以便以自对准方式从局部互连件在通孔中提供低电阻通路。