公开(公告)号：US6130481A

公开(公告)日：2000-10-10

申请号：US959457

申请日：1997-10-28

Applicant: Shigeru Harada ,  Kenji Kishibe ,  Akira Ihisa ,  Hiroshi Mochizuki ,  Eisuke Tanaka

Inventor： Shigeru Harada ,  Kenji Kishibe ,  Akira Ihisa ,  Hiroshi Mochizuki ,  Eisuke Tanaka

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/901 ,  Y10S257/904 ,  Y10S257/908 ,  Y10S257/915

Abstract: A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in the first electrically conducting interconnection layer proximate the through-hole extending to the first electrically insulating layer and filled with part of the second electrically insulating layer, constraining current flowing between the first and second electrically conducting interconnection layers to flow around the current barrier.A method of making a semiconductor integrated circuit interconnection structure includes forming an active electronic element in a semiconductor substrate; forming a first electrically insulating layer on the electronic element and the semiconductor substrate; forming a first electrically conducting interconnection layer electrically connected to the electronic element, at least partially disposed on the first electrically insulating layer, and including at least one opening extending to the first electrically insulating layer; forming a second electrically insulating layer on the first electrically conducting interconnection layer and filling the opening, thereby forming a barrier to the flow of current in a region of the first electrically conducting interconnection layer; forming a throughhole extending through the second electrically insulating layer to the first electrically conducting interconnection layer proximate the opening; and depositing a second electrically conducting interconnection layer on the second electrically insulating layer and in the through-hole, electrically contacting the first electrically conducting interconnection layer.

公开(公告)号：US4913090A

公开(公告)日：1990-04-03

申请号：US246742

申请日：1988-09-20

Applicant: Shigeru Harada ,  Masanori Obata ,  Eisuke Tanaka ,  Kenji Kishibe

Inventor： Shigeru Harada ,  Masanori Obata ,  Eisuke Tanaka ,  Kenji Kishibe

IPC: H01L21/205 ,  B01J12/02 ,  C03B19/00 ,  C23C16/455 ,  C23C16/54 ,  H01L21/31

CPC classification number: C23C16/54 ,  C23C16/455

Abstract: A single chamber apparatus for chemical vapor deposition of films on semiconductor substrates transported through the chamber. Heaters and a plurality of gas dispersing heads are disposed in the chamber for forming films by chemical vapor deposition. A cooling head is disposed between each adjacent pair of gas dispersing heads for cooling whereby the surface temperature of the substrates opposite the gas dispersing heads is substantially equal to that of the substrates located opposite the cooling heads.

Abstract translation: 用于化学气相沉积半导体衬底上的膜的单室装置，其通过室传送。 加热器和多个气体分散头设置在用于通过化学气相沉积形成膜的室中。 冷却头设置在相邻的一对气体分散头之间用于冷却，由此与气体分散头相对的基板的表面温度基本上等于与冷却头相对的基板的表面温度。

公开(公告)号：US4731516A

公开(公告)日：1988-03-15

申请号：US917124

申请日：1986-10-09

Applicant: Takeshi Noguchi ,  Yoshihiro Hirata ,  Junichi Arima ,  Eisuke Tanaka ,  Reiji Tamaki ,  Masanori Obata

Inventor： Takeshi Noguchi ,  Yoshihiro Hirata ,  Junichi Arima ,  Eisuke Tanaka ,  Reiji Tamaki ,  Masanori Obata

IPC: B23K26/00 ,  H01L21/20 ,  H01L21/268 ,  H01L21/304

CPC classification number: H01L21/268 ,  H01L21/2026 ,  Y10S117/904

Abstract: The rough ground rear surface 13b of a semiconductor wafer 11 is mirror-polished by localized irradiation with a focused laser beam 21. The wafer is moved relative to the beam, and the melt puddle formed by the beam thereafter recrystallizes at its trailing edge 24 to leave a mirror smooth rear surface 13c.

Abstract translation: 通过用聚焦激光束21的局部照射将半导体晶片11的粗糙的后表面13b镜面抛光。晶片相对于光束移动，并且由光束形成的熔融熔池随后在其后缘24处重结晶至 留下镜面光滑的后表面13c。

公开(公告)号：US4884120A

公开(公告)日：1989-11-28

申请号：US16787

申请日：1987-02-20

Applicant: Hiroshi Mochizuki ,  Reiji Tamaki ,  Junichi Arima ,  Masaaki Ikegami ,  Eisuke Tanaka ,  Kenji Saito

Inventor： Hiroshi Mochizuki ,  Reiji Tamaki ,  Junichi Arima ,  Masaaki Ikegami ,  Eisuke Tanaka ,  Kenji Saito

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L27/00 ,  H01L29/49

CPC classification number: H01L21/31683 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76888

Abstract: An improved interconnection structure and method for forming the interconnection in a semiconductor device having multilayered interconnection structure in which a contact hole for electrically connecting a first layer interconnection to a predetermined region of a semiconductor substrate and a through hole for electrically connecting a second layer interconnection to the first layer interconnection are formed in the regions overlapping with each other in planer layout. In the interconnection structure of the present invention, hillocks effective to compensate for the contact hole step are formed in the first layer interconnection only in the region of the contact hole of the first layer interconnection. In the method for forming the interconnection according to the present invention, a first layer interconnection is formed and a chemical conversion process is selectively performed to form a film which is more rigid than the first layer interconnection film on a predetermined region of the first layer interconnection film, and then a heat process is performed to generate hillocks only at the region of the contact hole of the first layer interconnection film. The second layer interconnection film is formed thereafter.

Abstract translation: 一种用于在具有多层互连结构的半导体器件中形成互连的改进的互连结构和方法，其中用于将第一层互连电连接到半导体衬底的预定区域的接触孔和用于将第二层互连电连接到 第一层互连形成在以平面布置彼此重叠的区域中。 在本发明的互连结构中，仅在第一层互连的接触孔的区域中，在第一层互连中形成有效补偿接触孔台阶的小丘。 在根据本发明的形成互连的方法中，形成第一层互连，并且选择性地执行化学转换处理以在第一层互连的预定区域上形成比第一层互连膜更刚性的膜 膜，然后进行热处理，仅在第一层互连膜的接触孔的区域产生小丘。 此后形成第二层互连膜。

公开(公告)号：US20070139034A1

公开(公告)日：2007-06-21

申请号：US11608298

申请日：2006-12-08

Applicant: Shuichi Takada ,  Eisuke Tanaka ,  Takeshi Abiru

Inventor： Shuichi Takada ,  Eisuke Tanaka ,  Takeshi Abiru

IPC: G01R31/28

CPC classification number: G01R31/275 ,  G01R31/2626

Abstract: According to the present invention, there is provided a semiconductor device having: a switching element serially connected to a resistive element to be measured; a plurality of transistors respectively connected in parallel to a series circuit consisting of the resistive element to be measured and the switching element, which will respectively take desired resistance values when turned on; and a measurement section which measures a resistance value of a parasitic resistance which occurs so as to be coupled to the resistive element to be measured by turning off the switching element and then controlling switching operations of the plurality of transistors to change the resistance values of resistors formed by the plurality of transistors, and subsequently measures a resistance value of the resistive element to be measured based on a resistance value of the parasitic resistance by turning on the switching element while turning off the plurality of transistors.

Abstract translation: 根据本发明，提供了一种半导体器件，其具有：与要测量的电阻元件串联连接的开关元件; 分别与由要测量的电阻元件和开关元件组成的串联电路并联连接的多个晶体管，其在接通时将分别获得期望的电阻值; 以及测量部分，其测量发生的寄生电阻的电阻值，以便通过关断开关元件而耦合到要测量的电阻元件，然后控制多个晶体管的开关操作以改变电阻器的电阻值 并且随后通过在断开多个晶体管的同时接通开关元件来基于寄生电阻的电阻值来测量要测量的电阻元件的电阻值。

公开(公告)号：US5712509A

公开(公告)日：1998-01-27

申请号：US873015

申请日：1992-04-24

Applicant: Shigeru Harada ,  Kenji Kishibe ,  Akira Ohisa ,  Hiroshi Mochizuki ,  Eisuke Tanaka

Inventor： Shigeru Harada ,  Kenji Kishibe ,  Akira Ohisa ,  Hiroshi Mochizuki ,  Eisuke Tanaka

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/901 ,  Y10S257/904 ,  Y10S257/908 ,  Y10S257/915

Abstract: A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting interconnection layer electrically connected to the electronic element and disposed at least partly on the first electrically insulating layer; a second electrically insulating layer disposed on the first electrically conducting interconnection layer; a second electrically conducting interconnection layer disposed on the second electrically insulating layer; and a through-hole penetrating the second electrically insulating layer to the first electrically conducting interconnection layer, part of the second interconnection layer being disposed within the through-hole and contacting the first electrically conducting interconnection layer wherein the first electrically conducting interconnection layer includes a current barrier including at least one opening in the first electrically conducting interconnection layer proximate the through-hole extending to the first electrically insulating layer and filled with part of the second electrically insulating layer, constraining current flowing between the first and second electrically conducting interconnection layers to flow around the current barrier.

Abstract translation: 半导体集成电路结构包括半导体衬底; 设置在所述基板中的电子元件; 设置在所述基板和所述电子元件上的第一电绝缘层; 电连接到所述电子元件并且至少部分地设置在所述第一电绝缘层上的第一导电互连层; 设置在所述第一导电互连层上的第二电绝缘层; 设置在所述第二电绝缘层上的第二导电互连层; 以及穿过所述第二电绝缘层到所述第一导电互连层的通孔，所述第二互连层的一部分设置在所述通孔内并与所述第一导电互连层接触，其中所述第一导电互连层包括电流 阻挡层，包括靠近通孔延伸到第一电绝缘层的第一导电互连层中的至少一个开口，并填充有第二电绝缘层的一部分，约束在第一和第二导电互连层之间流动的电流流动 围绕当前的障碍。