公开(公告)号：US11855043B1

公开(公告)日：2023-12-26

申请号：US17994205

申请日：2022-11-25

申请人： Eliyan Corporation

发明人： Ramin Farjadrad ,  Syrus Ziai

IPC分类号： H01L25/065 ,  H01L23/50

CPC分类号： H01L25/0655 ,  H01L23/50

摘要： A multi-chip module (MCM) includes a common substrate and first and second integrated circuit (IC) chips disposed on the common substrate. The first integrated circuit (IC) chip includes a first interface circuit disposed proximate a first edge of the first IC chip and a second interface circuit disposed proximate the first edge of the first IC chip. A first chiplet couples to the first interface circuit via a first link. A second chiplet couples to the second interface circuit via a second link. A first position of the first chiplet with respect to the first IC chip is staggered in a longitudinal dimension relative to a second position of the second chiplet with respect to the first IC chip.

公开(公告)号：US11841815B1

公开(公告)日：2023-12-12

申请号：US18092647

申请日：2023-01-03

申请人： Eliyan Corporation

发明人： Ramin Farjadrad

IPC分类号： G06F11/00 ,  G06F13/40 ,  H03M13/00 ,  H03M13/15

CPC分类号： G06F13/4027 ,  H03M13/1515 ,  H03M13/615

摘要： Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a first integrated circuit (IC) chip including a first interface defining a first number of interface contacts. Conversion circuitry receives a first full set of signals associated with the first interface and to omit a subset of the full set of signals to generate a reduced set of signals. Serialization circuitry serializes the reduced set of signals to generate a serialized set of signals. A second interface transmits the serialized set of signals with a second number of interface contacts that is less than the first number of interface contacts. A logic IC chip includes a third interface coupled to the second interface via a set of links and configured to match the second interface. Deserialization circuitry deserializes the serialized set of signals. Reconversion circuitry recreates signals corresponding to the omitted subset of the full set of signals and aggregates the recreated signals with the deserialized signals to form a second full set of signals that correspond to the first full set of signals.

公开(公告)号：US11893242B1

公开(公告)日：2024-02-06

申请号：US17994123

申请日：2022-11-25

申请人： Eliyan Corporation

发明人： Ramin Farjadrad ,  Syrus Ziai

IPC分类号： G06F3/06

CPC分类号： G06F3/0611 ,  G06F3/0629 ,  G06F3/0673

摘要： Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chip disposed on the common substrate. The first IC chip includes a first memory interface. A second IC chip is disposed on the common substrate and includes a second memory interface. A first memory device is disposed on the common substrate and includes memory and a first port coupled to the memory. The first port is configured for communicating with the first memory interface of the first IC chip. A second port is coupled to the memory and communicates with the second memory interface of the second IC chip. In-memory processing circuitry is coupled to the memory and controls transactions between the first memory device and the first and second IC chips.

公开(公告)号：US12058874B1

公开(公告)日：2024-08-06

申请号：US18528702

申请日：2023-12-04

申请人： Eliyan Corporation

发明人： Ramin Farjadrad

IPC分类号： H10B80/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11

CPC分类号： H10B80/00 ,  H01L25/0652 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/115

摘要： Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chiplet disposed on the common substrate. The first IC chiplet includes at least one processing element. A communications fabric switchably couples to the at least one processing element. A peripheral gearbox chiplet (PGC) includes a first port having a second memory-agnostic interface coupled to the first memory-agnostic interface of the first IC chiplet. The PGC includes a second port having a memory interface of a first type and interface conversion circuitry disposed between the second memory-agnostic interface and the memory interface of the first type.

公开(公告)号：US11842986B1

公开(公告)日：2023-12-12

申请号：US17973905

申请日：2022-10-26

申请人： Eliyan Corporation

发明人： Farjadrad Ramin

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L23/31 ,  H01L25/16 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/151 ,  H01L2924/181

摘要： Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and a first integrated circuit (IC) chip disposed on the package substrate. The first IC chip includes first core circuitry, and first interface circuitry for communicating with the first core circuitry. A second IC chip is disposed on the package substrate and includes second core circuitry and second interface circuitry for communicating with the second core circuitry. The second interface circuitry exhibits a non-matching interface with respect to the first interface circuitry. Interface adapter circuitry couples to the first interface circuitry and the second interface circuitry to establish a common physical interface (PHY) for communicating between the first core circuitry and the second core circuitry.